Technical Field

[0001] The present disclosure relates generally to semiconductor memory and methods, and more particularly, to a virtual register file.

Background

[0002] Memory devices are typically provided as internal,

semiconductor, integrated circuits in computing devices or other electronic devices. There are many different types of memory including volatile and nonvolatile memory. Volatile memory can require power to maintain its data (e.g., user data, error data, etc.) and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresi stive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.

[0003] Computing systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processor can comprise a number of functional units (e.g., herein referred to as functional unit circuitry (FUC)) such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and/or a combinatorial logic block, for example, which can execute instructions to perform logical operations such as AND, OR, NOT, NAND, NOR, and XOR logical operations on data (e.g., one or more operands).

[0004] A number of components in a computing system may be involved in providing instructions to the functional unit circuitry for execution. The instructions may be generated, for instance, by a processing resource such as a controller and/or host processor. Data (e.g., the operands on which the instructions will be executed to perform the logical operations) may be stored in a memory array that is accessible by the FUC. The instructions and/or data may be retrieved from the memory array and sequenced and/or buffered before the FUC begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the FUC, intermediate results of the operations and/or data may also be sequenced and/or buffered. In many instances, the processing resources (e.g., processor and/or associated FUC) may be external to the memory array, and data can be accessed (e.g., via a bus between the processing resources and the memory array) to execute instructions. Data can be moved from the memory array to registers external to the memory array via a bus.

[0005] A register file is an array of processor registers in a central processing unit (CPU). Integrated circuit-based register files may be

implemented, for example, by static random access memory (SRAM). The instruction set architecture of a CPU may define a set of registers used to stage data between memory and the FUC. The register file may be visible to the programmer, as opposed to the cache, which may not be visible to the programmer.

Brief Description of the Drawings

[0006] Figure 1 is a block diagram of an apparatus in the form of a computing system including at least one memory system in accordance with a number of embodiments of the present disclosure.

[0007] Figure 2 is a schematic diagram of a portion of a memory device in accordance with a number of embodiments of the present disclosure.

[0008] Figure 3 is a block diagram illustrating virtual register file memory translation according to a number of embodiments of the present disclosure.

Detailed Description

[0009] Given the complexity of modern computer architectures, software programmers and software tool chains (e.g., compilers, debuggers, etc.) can have more difficulty extracting efficient performance from a target platform. Adding processing in memory (PIM) devices can further complicate the architecture. Most modern computer architectures use a register-memory technique, where operations are executed in two separate domains. Logical operations (e.g., arithmetic, flow control, and combinatorial operations) are generally executed on a number of register files. Memory operations (e.g., load, store, etc.) are generally executed on memory devices. Instructions in register-memory architectures utilize register indices or memory addresses to indicate how/where to perform an operation.

[0010] PEVI computing architectures and/or devices can be classified as memory-memory devices in computing architecture taxonomies. This implies that both logical operations and memory operations are performed on the memory devices in-situ. Instructions in memory-memory architectures use physical addresses to indicate how/where to perform an operation.

[0011] Modern applications and operating systems use the notions of relocation and virtual addressing, which imply that an application can be loaded or relocated into different physical memory spaces due to the fact that the actual addressing is virtualized. The application and operating system reside in the virtual address space. The hardware and system architecture dereference these virtual addresses to their physical addresses when memory requests are made. However, any system architecture that includes the use of a PEVI device that natively relies on physical addressing conflicts with the notion of virtualizing memory.

[0012] Some embodiments of the present disclosure can expose low- level memory functionality provided by a PEVI device using a register-memory layer. This layer is referred to herein as a virtual register file. The ability to provide register-memory access to a PEVI device significantly decreases the level of customization that would otherwise be used in applications for the PEVI device via an optimizing compiler. Otherwise, the applications would be customized for each different kind of PEVI device or devices included in a system. Providing optimizing compilers and runtime systems with the ability to target what appears to be a register-memory architecture can greatly simplify an implementation that uses a PEVI device. Abstracting the physical addressing mechanisms of a PEVI device such that virtual addressing may sufficiently exist without collisions can be beneficial for integrating PIM devices with systems that generally operate on a register-memory architecture.

[0013] The present disclosure is related to a virtual register file. Source code can be compiled to include references to a virtual register file for data subject to a logical operation. The references can be dereferenced at runtime to obtain physical addresses of memory device elements according to the virtual register file. The logical operation can be performed in the memory device on data stored in the memory device elements.

[0014] In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how a number of embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, the designators "M" and "N", particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included. As used herein, "a number of a particular thing can refer to one or more of such things (e.g., a number of memory devices can refer to one or more memory devices). As used herein, the terms "first" and "second" are used to differentiate between one feature from another and do not necessarily imply an order between the features so designated.

[0015] The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 110 may reference element " 10" in Figure 1, and a similar element may be referenced as 210 in Figure 2. Multiple analogous elements within one figure may be referenced with a reference numeral followed by a hyphen and another numeral or a letter. For example, 240-1 may reference element 20-1 in Figure 2 and 240-N may reference element 40-N, which can be analogous to element 240-1. Such analogous elements may be generally referenced without the hyphen and extra numeral or letter. For example, elements 240-1,... , 240-N may be generally referenced as 440. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention, and should not be taken in a limiting sense.

[0016] Figure 1 is a block diagram of an apparatus in the form of a computing system 100 including at least one memory system 104 in accordance with a number of embodiments of the present disclosure. As used herein, a host 102, a memory system 104, a memory device 110, a memory array 111, and/or sensing circuitry 124 might also be separately considered an "apparatus."

[0017] The computing system 100 can include a host 102 coupled to memory system 104, which includes a memory device 110 (e.g., including a memory array 111 and/or sensing circuitry 124). The host 102 can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, or a memory card reader, among various other types of hosts. The host 102 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry), such as central processing unit (CPU) 106. The CPU 106 can be coupled to secondary storage 114 and to main memory 112 via a memory bus 1 16. The secondary storage 114 can be a storage device or other media not directly accessible by the CPU 106 such as hard disk drives, solid state drives, optical disc drives, and can be nonvolatile memory. The main memory 112 is directly accessible by the CPU 106. The main memory 112 can be volatile memory such as DRAM. The memory bus 116 can be analogous to the control bus 136 and the I/O bus 138, but for communication between the CPU 106 and the main memory 112 instead of for communication between the host 102 and the memory system 104. The CPU 106 can include a logic unit 118 coupled to a number of registers 120 and cache 122. The cache 122 can be an intermediate stage between the relatively faster registers 120 and the relatively slower main memory 112. Data to be operated on by the CPU 106 may be copied to cache 122 before being placed in a register 120, where the operations can be effected by the logic unit 118. Although not specifically illustrated, the cache 122 can be a multilevel hierarchical cache.

[0018] The computing system 100 can include separate integrated circuits or both the host 102 and the memory system 104 can be on the same integrated circuit. The computing system 100 can be, for instance, a server system and/or a high performance computing system and/or a portion thereof. Although the example shown in Figure 1 illustrates a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-Von Neumann architectures (e.g., a Turing machine), which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

[0019] For clarity, the computing system 100 has been simplified to focus on features with particular relevance to the present disclosure. The memory array 111 can be a hybrid memory cube (FDVIC), processing in memory random access memory (PFMRAM) array, DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The memory array 111 can comprise memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines). Although a single memory device 110 is shown in Figure 1, embodiments are not so limited. For instance, memory system 104 may include a number of memory devices 110 (e.g., a number of banks of DRAM cells).

[0020] The memory system 104 can include address circuitry 126 to latch address signals provided over an I/O bus 138 (e.g., a data bus) through I/O circuitry 130. Address signals can be received and decoded by a row decoder 128 and a column decoder 134 to access the memory device 110. Data can be read from the memory array 111 by sensing voltage and/or current changes on the sense lines using sensing circuitry 124. The sensing circuitry 124 can read and latch a page (e.g., row) of data from the memory array 111. The I/O circuitry 130 can be used for bi-directional data communication with host 102 over the I/O bus 138. The write circuitry 132 can be used to write data to the memory device 110. [0021] Controller 108 can decode signals provided by control bus 136 from the host 102. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control memory operations performed on the memory device 110, including data read, data write, and data erase operations. The signals can also be used to control logical operations performed on the memory device 110 including arithmetic, flow control, and combinatorial operations, among others. In various embodiments, the controller 108 is responsible for executing instructions from the host 102. The controller 108 can be a state machine, a sequencer, a processor, and/or other control circuitry.

[0022] An example of the sensing circuitry 124 is described further below in association with Figure 2. For instance, in a number of embodiments, the sensing circuitry 124 can comprise a number of sense amplifiers and a number of compute components, which may comprise a latch serving as an accumulator and that can be used to perform logical operations (e.g., on data associated with complementary sense lines). Logical operations can include Boolean operations (e.g., AND, OR, NOR, XOR, etc.), combinations of Boolean operations to perform other mathematical operations, as well as non-Boolean operations. In a number of embodiments, the sensing circuitry 124 can be used to perform logical operations using data stored in the memory array 111 as inputs and store the results of the logical operations back to the memory array 111 without transferring via a sense line address access (e.g., without firing a column decode signal). As such, a logical operation can be performed using sensing circuitry 124 rather than and/or in addition to being performed by processing resources external to the sensing circuitry 124 (e.g., by the host CPU 106 and/or other processing circuitry, such as ALU circuitry, located on the memory system 104, such as on the controller 108, or elsewhere).

[0023] In various previous approaches, data associated with a logical operation, for instance, would be read from memory via sensing circuitry and provided to registers 120 associated with the host CPU 106. A logic unit 118 of the host CPU 106 would perform the logical operations using the data (which may be referred to as operands or inputs) from the memory array 111 in the registers 120 and the result could be transferred back to the memory array 111 via the local I/O lines. In contrast, in a number of embodiments of the present disclosure, sensing circuitry 124 can be configured to perform a logical operation on data stored in memory cells in memory array 111 and store the result back to the array 1 11 without enabling a local I/O line coupled to the sensing circuitry and without using registers 120 of the host CPU 106.

[0024] As such, in a number of embodiments, registers 126 and/or a logic unit 118 of a host CPU 106 external to the memory array 111 and sensing circuitry 124 may not be needed to perform the logical operation as the sensing circuitry 124 can be operated to perform the logical operation using the address space of memory array 111. Additionally, the logical operation can be performed without the use of an external processing resource.

[0025] The host 102 can be configured with an operating system. The host 102 can be coupled to the memory device 110 (e.g., via the control bus 136 and/or the I/O bus 138). The operating system is executable instructions (software) that manages hardware resources and provides services other executable instructions (applications) that run on the operating system. The operating system can implement a virtual memory system.

[0026] According to the present disclosure, the CPU 106 can execute instructions to define a buffer in the main memory 112 of the host 102 with sufficient space to contain backing storage for a virtual register file (VRF) 117. The instructions can be executed to logically split the buffer into a number of virtual vector registers (VVR) 119, a number virtual scalar registers (VSR) 121, and a number of virtual control registers (VCR) 123, among other virtualized components as described herein, which collectively define the virtual register file 117. The host 102 can create the virtual register file 117 at runtime. These virtual registers 119, 121, 123 can represent a number of the registers 120 of the CPU 106 (e.g., physical vector registers, physical scalar registers, and/or physical control registers) for logical operations to be performed in the memory device 110. The virtual registers can represent physical registers 120 of the CPU 106 with respective indices to the virtual register file 117 at compile time as described in more detail in association with Figure 3. The virtual register file 117, specifically, the virtual vector registers 119 can store virtual addresses (e.g., base virtual addresses) of elements of the memory device 110 (e.g., the PEVI memory device 110 illustrated in Figure 1). A memory element (also referred to as a computational element) stores an amount of data that is operated on in one logical operation. The memory element can refer to a number of memory cells that store the amount of data. Memory-memory architectures may be prohibitively difficult to expose to high performance software and compiler implementations.

[0027] In some embodiments, the host 102 can include a memory management unit (MMU) 115. The MMU 115 is a hardware component that can perform translation between virtual memory addresses and physical memory addresses. That is, the MMU 115 can translate the virtual memory addresses stored in the virtual register file 117 to physical addresses of the elements of the memory device 110. Thus, the virtual register file 117 does not store the physical addresses of the elements of the memory device 110. In this regard, the virtual register file 117 does not need to be updated when data is moved within the memory device 110. Furthermore, unlike physical registers 120 associated with the CPU 106 for operations on data stored in the main memory 112, the virtual registers in the virtual register file 117 do not receive or store data corresponding to the elements of the memory device 110.

[0028] Figure 2 is a schematic diagram of a portion of a memory device

210 in accordance with a number of embodiments of the present disclosure. The memory device 210 is analogous to the memory device 110 illustrated in Figure 1. The memory device 210 can include a memory array 211 that includes memory cells 240-1, 240-2, 240-3, 240-4, 240-5, 240-6, 240-7, 240-8, ... , 240-N coupled to rows of access lines 242-1, 242-2, 242-3, 242-4, 242-5, 242-6, 242- 7, ... , 242-M and columns of sense lines 244-1, 244-2, 244-3, 244-4, 244-5, 244- 6, 244-7, 244-8, ... , 244-N. The memory array 21 1 is not limited to a particular number of access lines and/or sense lines, and use of the terms "rows" and "columns" does not intend a particular physical structure and/or orientation of the access lines and/or sense lines. Although not pictured, each column of memory cells can be associated with a corresponding pair of complementary sense lines.

[0029] Each column of memory cells can be coupled to sensing circuitry

224, which can be analogous to sensing circuitry 124 illustrated in Figure 1. In this example, the sensing circuitry includes a number of sense amplifiers 246-1, 246-2, 246-3, 246-4, 246-5, 246-6, 246-7, 246-8, ... , 246-N coupled to the respective sense lines 244. The sense amplifiers 246 are coupled to input/output (I/O) line 254 (e.g., a local I/O line) via access devices (e.g., transistors) 250-1, 250-2, 250-3, 250-4, 250-5, 250-6, 250-7, 250-8, ... , 250-N. In this example, the sensing circuitry also includes a number of compute components 248-1, 248-2, 248-3, 248-4, 248-5, 248-6, 248-7, 248-8,... , 248-N coupled to the respective sense lines 244. Column decode lines 252-1, 252-2, 252-3, 252-4, 252-5, 252-6, 252-7, 252-8, ... , 252-N are coupled to the gates of access devices 250 respectively, and can be selectively activated to transfer data sensed by respective sense amps 246 and/or stored in respective compute components 248 to a secondary sense amplifier 256. In a number of embodiments, the compute components 248 can be formed on pitch with the memory cells of their corresponding columns and/or with the corresponding sense amplifiers 246.

[0030] In a number of embodiments, the sensing circuitry (e.g., compute components 248 and sense amplifiers 246) is configured to perform a number of logical operations on elements stored in array 211. As an example, a first plurality of elements can be stored in a first group of memory cells coupled to a particular access line (e.g., access line 242-1) and to a number of sense lines 244, and a second plurality of elements can be stored in a second group of memory cells coupled to a different access line (e.g., access line 242-2) and the respective number of sense lines 244. Each element of the first plurality of elements can have a logical operation performed thereon with a respective one of the second plurality of elements, and the result of the logical operation can be stored (e.g., as a bit-vector) in a third group of memory cells coupled to a particular access line (e.g., access line 242-3) and to the number of sense lines 244.

[0031] Figure 3 is a block diagram illustrating virtual register file memory translation according to a number of embodiments of the present disclosure. The host (e.g., host 102 illustrated in Figure 1) can compile source code 360, such as C, C++, etc., with a compiler 362. The source code 360 can be compiled to include references to a virtual register file 317 for data subject to a logical operation. The compiler 362 can be configured to emit compiled code 364 (e.g., machine code, object code, etc.) with references to the virtual register file 317 in terms of indices to virtual vector registers in the virtual register file 317. The source code 360 can be compiled to target the virtual register file 317 for logical operations to be performed in the memory device 310 as though the logical operations were to be performed in the virtual register file 317 on the host (e.g., host 102 illustrated in Figure 1). That is, the virtual register file 317 can be targeted as though it was a physical register (e.g., physical register 120 illustrated in Figure 1) for the host device even though the actual logical operation is to be performed in the memory device 310 on the memory system (e.g., memory system 104 illustrated in Figure 1).

[0032] In order to provide functionality for programmers and compilers to generate code for the memory device 310, the virtual register file 317 is defined as the basis for the mapping between virtualized memory devices and the actual processing and memory hardware. Some previous source code compiler technology was made aware of or targeted a fixed set of mutable (changeable) hardware elements for the purpose of safe code generation. This hardware would generally include computational elements (e.g., logic unit 118 illustrated in Figure 1) and register files (e.g., registers 120 illustrated in Figure 1). However, the memory device 310 does not have mutable register files.

Operations are to be performed at or near the physical row and column intersection of the memory array (e.g., memory array 111 illustrated in Figure 1) or in the in-situ storage in the memory device (e.g., memory device 110 illustrated in Figure 1). If the memory device 310 were to function according to some previous compiler approaches, each memory cell in the memory device 310 would become a mutable and allocable hardware element, which could prevent applications from executing alongside one another in virtual memory.

[0033] The virtual register file 317 can virtualize access to the memory cells of the memory device 310. The virtual register file 317 can be stored in a buffer in memory (e.g., main memory 112 of a host 102 illustrated in Figure 1) and can function similar to a register file, except that the actual data to be operated on is not transferred to the virtual register file 317, or even to the host, because the operation is to be performed in the memory device 310 at runtime, rather than performing the logical operation with the host. The virtual register file 317 can be configured to store addresses of respective target elements rather than the actual data. There is no motivation to virtualize a physical register used according to some previous approaches because the physical register receives the data to be operated on by a logic unit of the host.

[0034] The entries in the virtual register file 317 can be translated at runtime from virtual address contents to respective physical addresses such that steps can be taken to initiate a logical operation using the memory device 310. Each element of the buffer that provides the backing storage for the virtual register file can be of a particular size (e.g., 64 bits) such that the buffer may be indexed analogously to a register file according to some previous approaches. The compiler 362 can be configured to target the virtual register file 317 as opposed to physical hardware entities (e.g., registers 120 illustrated in Figure 1) for operations to be performed in the memory device 310.

[0035] The compiled code 364 can include logical operations 368 and references 366 to the virtual register file 317, however the compiled code will not include a physical address corresponding to the virtual address associated with the virtual vector register. Some examples of the logical operations include add, subtract, multiply, etc. A particular reference 366 can be an index (e.g., %v0, %vl,... , etc.) to the virtual register file 317. A particular index can point to a virtual register in the virtual register file 317, such as a virtual vector register, a virtual scalar register, and/or a virtual control register, among others.

[0036] A respective index to the virtual register file 317 can represent a vector register or a scalar register with a fixed amount of backing storage of the virtual register file 317. A respective index to the virtual register file 317 can represent a control register with a variable amount of the backing storage.

Virtual addresses for elements of the memory device 310 can be stored in virtual vector registers of the virtual register file 317.

[0037] At runtime, the references to the virtual register file can be dereferenced (e.g., by virtual to physical translation 374) to obtain physical address of memory device elements. The dereferencing (e.g., virtual to physical translation 374) can include use of the runtime environment of the memory device 310 and/or use of a memory management unit of the host (e.g., the MMU 115 of the host 102 illustrated in Figure 1). The logical operation can then be performed in the memory device 310 on data that was stored in the memory device elements.

[0038] In some embodiments, the virtual register file 317 can also be used for memory operations (in addition to logical operations). For example, the source code 360 can be compiled to include a reference to the virtual register file 317 for data subject to a memory operation. The reference to the virtual register file can be dereferenced at runtime to obtain a physical address of a memory device element according to the virtual register file 317.

[0039] The following table illustrates an example of a virtual register file structure including indices, mnemonics, and descriptions of a number of components of the virtual register file:

Table 1

[0040] Although not specifically illustrated in the table above, the virtual register file 317 can store virtual addresses corresponding to physical addresses of elements of the memory device 310. In some embodiments, the virtual memory address can be a base virtual memory address, which in combination with a stored stride of memory device elements and a length of memory device elements together with the translated base virtual address, define which memory device elements correspond to the virtual vector register that stores the virtual memory address. However, the virtual register file 317 does not store physical addresses of the elements of the memory device 310.

[0041] Virtual to physical translation 374 can occur at runtime according to the runtime library 372, which can be part of the runtime environment of the host and/or the memory device 310. The translation can occur in response to a command calling for a logical operation to be performed in the memory device 310. For example, the compiled source code 364 can be executed to cause the logical operation to be performed in the memory device. The logical operation can be initialized according to a portion of the compiled source code 364 that addresses a particular virtual address. The logical operation can be performed in the memory device 310 on data stored in a particular physical address corresponding to the particular virtual address.

[0042] The runtime library 372 can be loaded by an application running on the host. For example, the runtime library 372 and the virtual register file 317 can be loaded into main memory of the host. Although not specifically illustrated as such, the runtime library 372 can create and/or contain the virtual register file 317 including virtual memory addresses of memory device elements. In some embodiments, each running thread can be associated with one virtual register file 317. The virtual register file 317 can be mapped to a particular memory bank of the memory device 310 at runtime, but can later be mapped to a different bank. For example, the memory device 310 can include multiple banks, each including a number of subarrays. The application that is running on the host can be relocated in the main memory of the host without editing the virtual register file 317, while maintaining the functionality provided by the virtual register file 317.

[0043] Although not specifically illustrated as such, a non -transitory computing device readable medium for storing executable instructions can include all forms of volatile and non-volatile memory, including, by way of example, semiconductor memory devices, DRAM, PEVI, HMC, EPROM, EEPROM, flash memory devices, magnetic disks such as fixed, floppy, and removable disks, other magnetic media including tape, optical media such as compact discs (CDs), digital versatile discs (DVDs), and Blu-Ray discs (BD). The instructions may be supplemented by, or incorporated in, ASICs. For example, any one or more of the secondary storage 114, the registers 120, the cache 122, the main memory 112, and/or the memory array 111 illustrated in Figure 1, can be a non-transitory computing device readable medium.

[0044] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

[0045] In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.