Title:
VOLTAGE-CONTROLLED OSCILLATION CIRCUIT AND PLL CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/085942
Kind Code:
A1
Abstract:
The present invention suppresses output noise. An adjustment circuit (4b) adjusts the oscillation frequency by changing, on the basis of a control signal (Vcnta), the capacitance values of variable capacitor elements (C1, C2) connected in parallel with an inductor (4a). An adjustment circuit (4c) adjusts the oscillation frequency by switching whether or not capacitor elements (C3, C4) are connected in parallel with the inductor (4a) by turning on or off a transistor (TR1) on the basis of a control signal (Vcntb). A switching circuit (4d) includes n-channel-type transistors (TR2, TR3) having drains thereof connected to the source or the drain of the transistor (TR1) and a power supply (VDD) via resistor elements (R1 to R5) and sources thereof connected to the ground. The bias voltage of the adjustment circuit (4c) is switched by switching on/off the transistors (TR2, TR3) on the basis of the control signal (Vcntb).
Inventors:
MATSUDA ATSUSHI (JP)
Application Number:
PCT/JP2016/060620
Publication Date:
May 26, 2017
Filing Date:
March 31, 2016
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H03B5/12; H03B5/08; H03L7/099; H03L7/10
Domestic Patent References:
| WO2008114455A1 | 2008-09-25 |
Foreign References:
| US20070247237A1 | 2007-10-25 | |||
| US20090184771A1 | 2009-07-23 | |||
| JP2013546228A | 2013-12-26 | |||
| JP2005529536A | 2005-09-29 | |||
| JP2006060395A | 2006-03-02 | |||
| JP2002314414A | 2002-10-25 |
Other References:
BODHISATWA SADHU ET AL.: "A Linearized, Low- Phase-Noise VCO-Based 25-GHz PLL With Autonomic Biasing", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 48, no. 5, May 2013 (2013-05-01), pages 1138 - 1150, XP011511090
Attorney, Agent or Firm:
HATTORI, Kiyoshi (JP)
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