Title:
VSB RECEIVER
Document Type and Number:
WIPO Patent Application WO2000019673
Kind Code:
A8
Abstract:
A loop gain of an AGC circuit (7) and a loop gain of a clock regenerative circuit (6) are kept increased (an amplifier gain is increased or a loop filter is set to a wide band) until a synchronizing signal (a segment synchronizing signal or field synchronizing signal) is detected. After a synchronizing signal is detected, a loop gain of the AGC circuit (7) and a loop gain of the clock regenerative circuit (6) are reduced (an amplifier gain is decreased or the loop filter is set to a narrow band). The above arrangements can make compatible the shortening of time required for completing a converging processing in the AGC circuit and the clock regenerative circuit with the increasing of ghost interference removal and an accurate clock regeneration.
Inventors:
KONISHI TAKAAKI (JP)
UEDA KAZUYA (JP)
AZAKAMI HIROSHI (JP)
UEDA KAZUYA (JP)
AZAKAMI HIROSHI (JP)
Application Number:
PCT/JP1999/005213
Publication Date:
May 04, 2000
Filing Date:
September 24, 1999
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD (JP)
KONISHI TAKAAKI (JP)
UEDA KAZUYA (JP)
AZAKAMI HIROSHI (JP)
KONISHI TAKAAKI (JP)
UEDA KAZUYA (JP)
AZAKAMI HIROSHI (JP)
International Classes:
H03L7/107; H04L27/08; H04N5/44; H04N5/52; H04N5/21; (IPC1-7): H04L27/06
Download PDF:
Previous Patent: A ROUTING ARRANGEMENT
Next Patent: CONVERSION OF GFSK-MODULATED SIGNALS INTO QPSK-MODULATED SIGNALS
Next Patent: CONVERSION OF GFSK-MODULATED SIGNALS INTO QPSK-MODULATED SIGNALS