Title:
WAFER DISPATCHING METHOD AND ELECTRONIC DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/088294
Kind Code:
A1
Abstract:
Provided are a wafer dispatching method and an electronic device. The wafer dispatching method comprises: when a simulation dispatching sequence runs to a test wafer dispatching time point, determining a target wafer to be processed, the simulation dispatching sequence being used for dispatching wafers to be processed (101); rolling back the simulation dispatching sequence to a target wafer to be processed dispatching time point corresponding to the target wafer to be processed (102); and setting a test wafer process path on the target wafer to be processed dispatching time point, and generating an executable dispatching sequence (103). When a test wafer needs to be dispatched, a wafer to be processed at this time is determined, rollback to a target wafer to be processed dispatching time point is enabled, and a test wafer process path is set at the target wafer to be processed dispatching time point, so that the test wafer is first dispatched at this time. Therefore, when the test wafer is required to enter a processing chamber, the test wafer in the process path can be quickly used, the idle waiting time is saved, and the productivity of semiconductor chips is improved.
More Like This:
Inventors:
LI JIE (CN)
ZHANG LU (CN)
LIU MUYA (CN)
ZENG WEIPENG (CN)
ZHANG LU (CN)
LIU MUYA (CN)
ZENG WEIPENG (CN)
Application Number:
PCT/CN2023/126409
Publication Date:
May 02, 2024
Filing Date:
October 25, 2023
Export Citation:
Assignee:
BEIJING NAURA MICROELECTRONICS EQUIPMENT CO LTD (CN)
International Classes:
G06F11/22; G06Q10/0631
Foreign References:
| CN115794506A | 2023-03-14 | |||
| CN105185731A | 2015-12-23 | |||
| CN101459098A | 2009-06-17 | |||
| US6122566A | 2000-09-19 | |||
| US5928389A | 1999-07-27 |
Attorney, Agent or Firm:
TEE & HOWE INTELLECTUAL PROPER TY ATTORNEYS (CN)
Download PDF: