[0001] The present invention relates to methods and apparatus for grading a semiconductor material, for instance wafers for photovoltaic cell manufacture, and optionally sorting the graded wafers into a smaller number of classifications. It will be appreciated, however, that the invention is not limited to this particular field of use.

Related Applications

[0002] The present application claims priority from Australian Provisional Patent

Application No 201 1904618, filed on 7 November 201 1, the contents of which are incorporated herein by reference.

Background of the Invention

[0003] Any discussion of the prior art throughout this specification should in no way be considered as an admission that such prior art is widely known or forms part of the common general knowledge in the field.

[0004] Commercial wafer based photovoltaic (PV) cells are made from typically 10x10 cm ² up to 22x22 cm silicon wafers. As illustrated in Fig 1, a cast multi crystalline silicon block 2 (also known as an ingot), typically 1x1x0.7 m ³ in size, is sawn into square (10x10 cm ² up to 22x22 cm ² ) shaped columns 4 (commonly known as bricks), which are then sawn into individual wafers 6, each typically 120-250 μπι thick. An ingot is usually sawn into 4x4 or 5x5 bricks. PV cells can be made from multicrystalline silicon or monocrystalline silicon, with different techniques used for growing multicrystalline and monocrystalline silicon ingots.

[0005] A variety of defects appear in the silicon during crystallisation and ingot growth, including impurities, inclusions and structural defects such as decorated and undecorated dislocations and grain boundaries. Since these defects are often recombination active, i.e. they act as sites for recombination of electrons and holes, which reduces the minority carrier lifetime, their distribution and density in bricks and wafers is of great interest to PV cell and wafer manufacturers. [0006] Levels of doping can vary from ingot to ingot and also within an ingot in some manufacturing processes. Therefore, wafers may have different dopant levels and this is known to have an impact on the efficiency or performance of the PV cells made from such wafers.

[0007] Imaging of band-to-band photoluminescence (PL), using apparatus described in published PCT patent applications Nos WO 2007/041758 Al and WO 201 1/079354 Al, has been shown to be useful for revealing impurity-rich regions and recombination active defects in silicon wafers, because of the dependence of PL intensity on minority carrier lifetime. It has also been shown that PL measurements along side facets of bricks can reveal defect- or impurity-rich regions, which can be used as a wafer cutting guide. Other known techniques for characterising silicon block and wafer samples include infrared (IR) transmission for determining the density and position of inclusions such as silicon carbide and silicon nitride, resistivity measurements for determining the background doping density at one or more points, and techniques such as transient or quasi steady state photoconductance (QSSPC) and microwave photoconductance decay (μ-PCD) that measure the effective or surface limited minority carrier lifetime at one or more points.

[0008] Published PCT patent application No WO 2009/ 121133 Al discusses the concept of acquiring PL images of silicon wafers, then assessing the density of defects such as dislocations and using that information for a variety of purposes including checking incoming wafer quality, sorting wafers into quality bins, improving the bulk silicon casting process, and predicting one or more operational parameters of PV cells manufactured from the wafers. An approximate correlation between relative dislocation density and open circuit voltage was shown, however there are clearly improvements to be made in this predictive aspect.

[0009] While some recombination active defects and impurities can be removed or ameliorated during PV cell manufacture, e.g. gettering in the emitter diffusion step or back metallisation, or hydrogen passivation in the silicon nitride process step, many defects produced during ingot crystallisation remain in the silicon and limit cell efficiency. Furthermore some types of defects appear to become more recombination active during cell manufacture, activated perhaps during annealing. An improved understanding of the distribution, density and type of defects in bricks or wafers, and of defect removal or activation during cell manufacture, would therefore be of value throughout the P V cell supply chain. [0010] It follows that the properties of a semiconductor material, e.g. wafers, are to some extent a predictor of the performance and/or efficiency of a resultant photovoltaic device.

However there are a large number of additional factors which can affect the performance and efficiency of photovoltaic devices, not the least of which is the type and conditions of the particular cell line on which the PV devices are produced. To explain, one could provide an identical semiconductor wafer to two different cell lines and the resultant PV devices may have quite different performance characteristics.

[0011] Further, as will be appreciated by a person skilled in the art, it is highly desirable for a cell manufacturer to have consistent source material or at least be able to minimise variations in the source material i.e. wafers entering the cell line. More desirable is that all cells have the highest possible efficiency taking into account the inherent limitations of the starting wafers, specifically with respect to performance limiting defects therein.

Summary of the Invention

[0012] It is an object of the present invention to overcome or ameliorate at least one of the disadvantages of the prior art, or to provide a useful alternative. It is an object of the present invention in a preferred form to provide a protocol for grading silicon wafers based on one or more measured properties of the wafers. It is another object of the present invention in a preferred form to provide improved methods for measuring the distribution, intensity, density or type of defects in silicon in bulk and wafer form, and for using that information to provide improved performance of silicon PV cells.

[0013] In a first aspect the present invention provides a method of grading a plurality of samples of a semiconductor material for manufacturing photovoltaic cells, said method comprising:

(a) subjecting each sample to a photoluminescence-based analysis comprising generating and imaging photoluminescence from said material;

(b) subjecting each sample to one or more non-photoluminescence-based analyses;

(c) processing data obtained from said photoluminescence-based analysis and said one or more non-photoluminescence-based analyses to obtain information on one or more - properties of said samples; and (d) grading said samples into a predetermined number of grades based on said one or more properties.

[0014] In certain embodiments the one or more non-photoluminescence-based analyses comprise measuring one or more of resistivity, thickness or carrier lifetime at one or more points across a sample. Preferably the one or more non-photoluminescence-based analyses obtain data at a plurality of points along one or more lines across a sample. The one or more non-photoluminescence-based analyses preferably obtain two or more data sets at the same points across a sample. Alternatively, the one or more non-photoluminescence-based analyses obtain two or more data sets at different points across a sample, and the method further comprises the step of bringing the data sets into spatial registration by interpolation or extrapolation.

[0015] In certain embodiments the one or more non-photoluminescence-based analyses comprises optical imaging. The optical imaging is preferably conducted using multiple illumination sources and camera measurements. Preferably, at least some of the illumination sources emit light of differing wavelengths. More preferably, optical images are acquired with a colour sensitive camera. In preferred embodiments information on crystal grain structure in the samples is obtained from one or more optical images, optionally in combination with one or more photoluminescence images.

[0016] Preferably, the properties are selected from the group comprising: bulk carrier lifetime; effective carrier lifetime; density, area fraction or total length of grain boundaries; average crystal grain size; crystal grain size distribution; total number of crystal grains; area fraction of the largest grain; density, intensity, or area fraction of dislocations; background doping level; area fraction or severity of impurity-rich regions; thickness; surface roughness; scratches; chips; and number or total length of cracks.

[0017] The grade assigned to a sample is preferably indicative of one or more performance characteristics of a photovoltaic cell to be manufactured from the sample, the characteristics comprising one or more of open circuit voltage, short circuit current, efficiency, fill factor, service lifetime, or mechanical or electrical performance characteristics. Alternatively, the grade assigned to a wafer is indicative of its economic value, or of its suitability for a given photovoltaic cell manufacturing process.

[0018] Preferably, the method further comprises providing a plurality of classifications for the samples, the number of the classifications being less than the predetermined number of grades, wherein samples from one or more grades are sorted into each classification. The sorting may comprise physical separation of the samples into two or more bins. [0019] Preferably, the photoluminescence-based analysis provides data on one or more of:

(i) dislocations in said samples;

(ii) impure region area and intensity in said samples; and

(iii) photoluminescence intensity from said samples.

[0020] In certain embodiments the photoluminescence intensity data, combined with thickness and resistivity data, provides information on the effective lifetime of the samples. In alternative embodiments the photoluminescence intensity data, combined with thickness and effective lifetime data, provides information on the doping level of the samples. [0021 ] In a second aspect the present invention provides a grading protocol for grading the utility of a plurality of samples of a semiconductor material in the manufacture of photovoltaic cells, said protocol comprising: conducting at least two analyses of said samples comprising a photoluminescence imaging analysis and one or more non-photoluminescence-based analyses; processing data from said analyses to obtain information on one or more properties of said samples; and assigning a grade to each said sample based on said one or more properties.

[0022] In certain embodiments the one or more non-photoluminescence-based analyses comprise measuring one or more of resistivity, thickness or carrier lifetime at one or more points across a sample. In other embodiments the one or more non-photoluminescence-based analyses comprises optical imaging. In preferred embodiments information on crystal grain structure in the samples is obtained from one or more optical images, optionally in combination with one or more photoluminescence images.

[0023] In a third aspect the present invention provides a method of manufacturing photovoltaic cells from a graded population of wafers, said method comprising: a) allocating said wafers into a number of classifications, each classification receiving one or more grades of wafers; and

b) manufacturing photovoltaic cells from wafers in a respective classification,

wherein said grades of wafers allocated to a respective classification are based on

predetermined performance criteria related to the respective photovoltaic cell manufacture line.

[0024] In a fourth aspect the present invention provides a method of manufacturing photovoltaic cells from a graded population of wafers, said method comprising:

a) allocating said wafers into a number of classifications, each classification

receiving one or more grades of wafers, and

b) manufacturing photovoltaic cells from wafers in a respective classification,

wherein process parameters or settings of the respective photovoltaic cell manufacture line are chosen based on the classification of said wafers.

[0025] Preferably, grades of wafers are chosen for sorting into classifications based on a requirement that all wafers in a respective classification will produce photovoltaic cells having an efficiency variance of less than ¾, preferably less than ½, and more preferably less than 1/3 of the efficiency variance of photovoltaic cells produced from an ungraded and unsorted population of wafers.

[0026] Additionally, once the aforementioned wafers are graded as proposed, the present invention may provide additional advantages by sorting the graded wafers. To explain, it would clearly be inefficient to have an infinite number of wafer grades as this would provide very little control or improvement on the source material for PV cell production. Accordingly, it is preferred that the number of wafer grades be maintained below a predetermined level, e.g. up to 30 or even 100 grades. Even this number of grades, however, can provide significant variation in the source material for the PV cell manufacturing line. The present invention also provides an optional sorting protocol whereby the semiconductor material/wafers are sorted into a number of classifications that is smaller than the number of grades. In other words, at least some of the classifications will contain more than one grade of wafer. Classification may involve physical separation of the wafers into separate 'bins', or virtual separation. A manufacturer may then 'calibrate' their manufacturing lines or line with the source material, i.e. wafer grade or classification. In a particularly preferred embodiment, the 'borders' of the classifications are maintained within reasonably tight tolerances such that variation between the relevant properties of the graded wafers within a classification is reduced.

[0027] Not only do the aforementioned methods and apparatus provide for grading semiconductor material, e.g. wafers, in a cost effective and timely fashion, they also provide the opportunity for significant benefits in manufacturing photovoltaic cells by providing a graded population of wafers as a source material for the PV cell lines. This in turn allows

manufacturers to optimise their cell lines, yielding still further process benefits.

[0028] Throughout the specification we use the term 'grading" to refer to the process of assigning to a wafer a grade based on information measured either on the wafer itself or on the brick or ingot from which it was cut. By 'wafers' we mean as-cut wafers or wafers that have been partially processed into devices such as PV cells. Amongst other factors, grading may be based on quantitative information on the distribution, intensity or density of specific types of defects that are known or at least are suspected to have an impact on PV cell performance.

[0029] The term 'sorting' is used throughout the specification to refer to assigning and possibly physically separating wafers into a number of classifications or bins based on the aforementioned grading or grade. These classifications or bins can involve physical separation, or virtual separation if wafer tracking is enabled. For example the best quality wafers, e.g. wafers with relatively few dislocations, low impurities and few inclusions, can be assigned to a high efficiency cell line and moderate quality wafers to a standard cell line, while highly defective wafers, e.g. wafers with cracks or high impurity levels, can be rejected. Alternatively or additionally, wafers may be sorted according to the predominant type of defect detected. Wafer sorting is most likely to be performed by a cell manufacturer, but could also be performed by a wafer manufacturer.

[0030] The relationship between grading and sorting for a given PV cell line will depend on one or more factors including the type or source of wafers, the cell design, and the cell process toolset and process conditions. If a PV cell line has wafer to cell tracking capability, physical sorting of wafers into quality classifications or bins may be unnecessary, or may be simplified, i.e. using fewer quality bins. It may also be possible to sort completed cells into classifications based on grades assigned to incoming wafers, or to use the grades as additional data for conventional end-of-line cell testing. Wafer grading can be used for purposes other than sorting, such as wafer pricing, feed forward to cell process monitoring or cell process settings, or feed back to the silicon casting process. In preferred embodiments PL imaging techniques are used to obtain the defect-related information for wafer grading, but many other

measurement techniques may be useful for obtaining information on defects or some other wafer property.

[0031 J In a fifth aspect the present invention provides an apparatus for grading a plurality of samples of a semiconductor material for manufacturing photovoltaic cells, said apparatus comprising:

a) a first analysis system adapted to generate and capture a photoluminescence image of each sample;

b) at least one second analysis system adapted to analyse at least one non- photoluminescence characteristic of each sample;

c) a processor adapted to receive and process data from said first and second analysis

systems and provide information on one or more properties of said samples; and d) a grading device operatively associated with said processor adapted to assign, based on said one or more properties, one of a predetermined number of grades to each sample of said semiconductor material.

[0032] In certain embodiments the at least one second analysis system is adapted to measure one or more of resistivity, thickness or carrier lifetime at one or more points across a sample. Preferably the at least one second analysis system is adapted to obtain data at a plurality of points along one or more lines across a sample. The at least one second analysis system is preferably adapted to obtain two or more data sets at the same points across a sample.

Alternatively, the at least one second analysis system obtains two or more data sets at different points across a sample, and the processor is adapted to bring the data sets into spatial registration by interpolation or extrapolation.

[0033] In certain embodiments the at least one second analysis system comprises an optical imaging system. The optical imaging system preferably comprises multiple illumination sources and at least one camera. Preferably, at least some of the illumination sources emit light of differing wavelengths. More preferably, the at least one camera comprises a colour sensitive camera. In preferred embodiments the processor is adapted to provide information on crystal grain structure in the samples from one or more optical images, optionally in combination with one or more photoluminescence images.

[0034] Preferably, the analysis systems are adapted to provide data on one or more properties selected from the group comprising: bulk carrier lifetime; effective carrier lifetime; density, area fraction or total length of grain boundaries; average crystal grain size; crystal grain size distribution; total number of crystal grains; area fraction of the largest grain; density, intensity or area fraction of dislocations; background doping level; area fraction or severity of impurity- rich regions; thickness; surface roughness; scratches; chips; and number or total length of cracks.

[0035] Preferably, the apparatus further comprises a classifier for sorting the graded samples into a plurality of classifications, wherein the number of the classifications is less than the predetermined number of grades. The apparatus may further comprise a transfer mechanism for physically separating the classified samples into two or more bins.

[0036] In a sixth aspect the present invention provides a system for manufacturing photovoltaic cells from semiconductor wafers, said system comprising an apparatus according to the fifth aspect above with at least one photovoltaic cell line downstream thereof, said cell line being operatively associated with said apparatus such that the grade assigned to a wafer and one or more process parameters applied to said wafer in the cell line are calibrated to obtain a photovoltaic cell with predetermined IV characteristics.

[0037] In a seventh aspect the present invention provides a computer usable medium having a computer readable program code configured to implement the method according to the first, third or fourth aspects above, or to apply the grading protocol according to the second aspect above, or to operate the apparatus according to the fifth aspect above, or to operate the system according to the sixth aspect above.

Brief Description of the Drawings

[0038] Benefits and advantages of the present invention will become apparent to those skilled in the art to which this invention relates from the subsequent description of exemplary embodiments and the appended claims, taken in conjunction with the accompanying drawings, in which:

[0039] Fig 1 illustrates the sawing of a silicon ingot into bricks and wafers;

[0040] Fig 2 shows a PL image of a wafer cut from a multicrystalline silicon brick;

[0041] Fig 3 shows the PL image of Fig 2 with line-shaped features highlighted;

[0042] Fig 4 shows the PL image of Fig 2 with dislocation-type features highlighted;

[0043] Figs 5.1 and 5.2 show PL images of wafers cut from different positions within a multicrystalline silicon 'edge' brick;

[0044] Fig 6 shows a grading flowchart in accordance with a preferred embodiment of the invention;

[0045] Fig 7 shows a grading system spreadsheet in accordance with a preferred embodiment of the invention;

[0046]. Fig 8 shows a sorting system in accordance with a preferred embodiment of the invention, where graded wafers are sorted into a lesser number of bins according to expected cell performance;

[0047] Figs 9A and 9B show in schematic side and top views a wafer sorting tool according to a preferred embodiment of the invention;

[0048] Fig 10 shows possible transport mechanism structures in a wafer sorting tool according to an embodiment of the invention;

[0049] Figs 1 1 and 12 show an optical reflection image and a PL image respectively of a cast monocrystalline silicon wafer;

[0050] Fig 13 shows in schematic side view a system for acquiring PL and reflection images of a silicon wafer; [0051] Fig 14 shows in schematic side view a system for simultaneously acquiring multiple colour images of a silicon wafer; and

[0052] Fig 14A shows the arrangement of RGB colour filters on the pixels of a colour line camera.

Detailed Description

[0053] Preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings.

[0054] As mentioned above, the present invention relates to a method and apparatus for grading semiconductor material, in particular wafers, and producing photovoltaic devices from a graded population of wafers.

[0055] There are a variety of techniques for analysing semiconductor materials. In particular the present Applicant has developed various photoluminescence (PL) imaging techniques for analysing silicon wafers and partially or fully fabricated photovoltaic cells. The present invention involves the use of these PL imaging techniques in combination with one or more non-PL-based techniques to obtain information on one or more properties of a population of silicon wafers.

[0056] A wide variety of properties can be measured including bulk carrier lifetime and spatial variations thereof, effective carrier lifetime and spatial variations thereof, the density or area fraction of crystal grain boundaries, the size distribution or total number of crystal grains, the size or area fraction of the largest grain, the density, intensity or area fraction of dislocations, background doping level and variations thereof, wafer thickness or thickness variation, area fraction or severity of impurity-rich regions, scratches, chips, saw marks and the number or total length of cracks. A grading of the semiconductor material based on the one or more properties is then provided, i.e. each wafer is allocated one of a predetermined number of grades. In preferred embodiments the grading protocol is designed to include some or all of the relevant measurable properties that could have an impact on photovoltaic cell performance, so that the grades are indicative of one or more performance characteristics of photovoltaic cells to be manufactured from the graded wafers. These performance characteristics can include open circuit voltage, short circuit current, efficiency, fill factor, service lifetime, or mechanical or electrical performance characteristics or the like. In other embodiments the grades are indicative of wafer aesthetics, for which the relevant properties may include surface stains, chipped corners, saw marks or scratches, or of economic value, or of the suitability of a wafer for a given cell manufacturing process.

[0057] In preferred embodiments the non-PL-based analysis techniques include one or more of a resistivity measurement, a thickness measurement, a transient or steady state lifetime measurement or a doping type measurement at one or more sampling points, or optical imaging.

[0058] Based on the combined data obtained by the aforementioned or other analysis techniques, along with suitable processing of the data, a grade is assigned to the wafer being analysed. For a grading protocol based on features known or at least suspected to have an impact on PV cell performance, it is expected that wafers of a certain grade will each be made into cells with similar performance. As will be clear to a person skilled in the art however, ultimately the actual performance of a photovoltaic cell will also depend on a number of additional factors unrelated to the wafers, such as settings and fluctuations on the cell manufacturing line (which may vary in time) and the cell design concept. However, by data acquisition and correlation of the measured data with the performance of the photovoltaic cells thus produced, one can provide more consistent correlation between grades of wafers and resultant efficiency/performance of a photovoltaic cell produced from the respective grades of wafers on a specific line with a specific set of conditions.

[0059] There are a number of advantages arising from grading the wafers. The first of course is the ability to separate the wafers into grades related to expected cell performance, such that when wafers of a given grade are passed through the cell production line the current- voltage (IV) performance of the resultant photovoltaic cells is relatively consistent. In other words, instead of having a PV cell line producing cells with substantial variation in

performance due to variation in the incoming wafers, the present invention provides a mechanism for grading wafers and thereby providing a more consistent source material for the cell line.

[0060] The data to be collected is also open to choice by the relevant party e.g. wafer manufacturer or cell manufacturer. In other words, a cell manufacturer may be aware of what aspects of the semiconductor material are most relevant to the performance/efficiency of its cells. It will be these parameters which are most important to that particular cell manufacturer, and they may wish to measure, grade and/or sort the wafers based upon their own

predetermined criteria. In the alternative, a wafer manufacturer or cell manufacturer may be provided with a 'generic' system analysing some or all potentially relevant criteria in a semiconductor material. This processed data can then be correlated over time to cell efficiency /performance such that the wafer manufacturer or cell manufacturer is made aware of which criteria have the most beneficial or detrimental effect on the ultimate performance of the PV cells produced from the semiconductor materials in a particular cell line.

[0061] It should be stressed that the present invention is not only suitable for cell

manufacturers but also for wafer manufacturers. There is significant economic benefit in wafer manufacturers grading their wafers for later sale, and they may be able to tailor the grade of their wafers for a particular cell manufacturer. For instance, if a cell manufacturer wishes to produce high cost, high efficiency PV devices, they will obviously require the grade of wafers which will provide such a result when used in their cell line. Another cell manufacturer on the other hand may find that grade of wafers to be less suitable to their particular cell line. Still further, a cell manufacturer who wishes to produce PV cells of lower efficiency and lower cost may be able to use another grade of wafer which, presumably, would be sold at a lower cost. The ability of a wafer manufacturer to provide such a consistent and tailored source of wafers to a PV cell manufacturer has significant economic and technical benefits.

[0062] As mentioned above, and as will be described in more detail below, many key properties of wafers and blocks can be measured before commencing cell manufacture. For example PL imaging and processing can determine the area fraction, size, shape, frequency, intensity or other factors relating to a number of features including dislocations, impure regions, cracks, chips and crystal grain boundaries. Measurements of PL intensity (also known as PL count) can be combined with other measurement data to give information on other material properties. For example PL intensity measurements can be combined with effective lifetime data to give information on the doping levels in a wafer, or with doping level data to give information on effective lifetime, from which one can infer impurity concentration. Wafer thickness or thickness variation measurements are also useful, e.g. for normalising PL intensity to take into account variations in the volume of silicon present, or for converting resistivity data to doping data. Other useful techniques include optical reflection imaging for detecting grain boundaries, the size distribution of grains and particularly the size of the largest grain, and physical defects in a wafer such as chips and scratches, infrared transmission for the detection of inclusions, and quasi-steady state photoconductance and transient photoconductance decay, both of which can give information related to the lifetime or spatially resolved lifetime of a wafer.

[0063] It is this type of information that, when measured and processed, can be used to grade wafers. The purpose of grading wafers is many-fold but generally revolves around the fact that each grade of wafers, if run through a production line, would produce cells with different electrical performance, i.e. different IV characteristics. Since the IV characteristics of a cell determine its economic value, this is an important capability. The grading of wafers involves measuring quantities as determined by PL imaging and at least one non-PL-based measurement as described above, and processing the measurement data into metrics useful for grading wafers. These metrics include the determination of values related to known defect types in wafers and/or other properties known or at least suspected to affect the IV characteristics of cells. By way of example a wafer may have a series of values assigned to it relating to the doping level, the area fraction and type of dislocations, the area fraction and intensity of impurity-rich regions and the like.

[0064] One important additional characteristic for so-called cast monocrystalline wafers is crystal grain structure i.e. the degree of monocrystallinity or multicrystallinity of a wafer, which can be inferred from optical reflectivity measurements or IR transmission measurements, described in this document generically as grain boundary detection. The highest value wafers are fully monocrystalline, since these can be textured differently to multicrystalline wafers to give a higher performance cell. Fully or largely multicrystalline wafers have lower value, and mixed wafers say with a large single grain region and a region of multicrystallinity can fall somewhere in between in value. Consequently, a wafer grading system for cast

monocrystalline wafers may include a further property related to the degree of

monocrystallinity, e.g. area fraction of the monocrystalline portion.

[0065] As will be discussed in more detail below, the number of wafer grades can be chosen as required. Simple grading protocols may have only two or three grades, while more sophisticated protocols may have of order five, 20, 30 or even 100 grades. Graded wafers can also be sorted into a number of classifications or bins, with this number being fewer than the number of grades. The number of bins can be left to individual cell manufacturers who would of course have a more intimate understanding of their manufacturing processes. For example wafers may be graded into 20 or more different types of wafers based on five levels of dislocations and four levels of impurities, which may be reduced by sorting into say six bins. A manufacturer can then 'calibrate' the relationship between wafer grading types or sorted 'bins' of wafers and typical cell performance by running trials. Over time the number of bins might be further reduced for practical purposes since under typical conditions for that manufacturer some of the bins end up producing cells with similar performance even though the wafers in those combined bins have different measured properties.

[0066] Before describing specific examples of wafer grading schemes, we will present and discuss a number of PL images to demonstrate how some key metrics are determined. Fig 2 shows a PL image of a typical p-type multicrystalline silicon wafer, showing a large number of dark features indicative of non-radiative recombination sites such as dislocations and grain boundaries. The relative PL intensity reflects the severity of these features in terms of carrier lifetime reduction, which is typically worsened by decoration with metal species such as neutral metal or metal silicides. In favourable circumstances it may be relatively simple for a trained operator or an image processing algorithm to distinguish dislocation clusters 8 from grain boundaries 10, but in other cases it can be difficult to distinguish these defects from each other, or from other recombination centres such as distributed impurities (e.g. metal ions diffusing into the silicon from the melt crucible), silicide inclusions and cracks.

[0067] A PL image such as that shown in Fig 2 can be analysed with a number of algorithms of varying sophistication to obtain information for wafer grading or sorting, which can be fed forward to improve a cell process. Alternatively the information can be fed backward to improve a block or ingot casting process. At a basic level, since a greater area density of recombination active defects in a wafer generally correlates with lower efficiency when made into a PV cell, a simple quantification of the number of pixels with relative PL intensity (or PL count) below a threshold can be used as a quality metric. More sophisticated algorithms may attempt to distinguish between different types of defect, e.g. on the basis of shape or intensity, bearing in mind that a darker (and therefore more recombination active) feature may have more impact on cell performance than a lighter feature of similar size, or may apply high pass filtering to suppress long range intensity changes caused by background doping variations for example, or may normalise the PL intensity for background doping, wafer thickness or either bulk or effective lifetime, among many possibilities. In one embodiment PL intensity is normalised using measured resistivity as a proxy for background doping. The conversion of resistivity to doping can be done either qualitatively (using the inverse of resistivity) or quantitatively, taking into account the carrier density dependent mobility, e.g. from a lookup table or an analytical expression. In preferred embodiments, image processing algorithms will analyse and report a variety of metrics related to different types of defect, such as average size, size distribution and number of defects in a wafer. For example for dislocations the metrics may include size, shape, average density and intensity of dislocations and total area or length of dislocations. Metrics related to crystal grain structure, such as average grain size, grain size distribution, number of grains in a wafer and total length of grain boundaries in a wafer may also be useful for grading multicrystalline wafers. Other important metrics include the area fraction and intensity of high impurity regions, as well as the background doping level in the silicon and variations in this quantity.

[0068] By way of specific example, Fig 3 shows an overlay that highlights the position of line-shaped features in the PL image of Fig 2 with relative PL intensity below a certain threshold, identified by an edge detection algorithm for example. In another example, Fig 4 shows an overlay that highlights features that have the appearance of dislocations. Comparison between the two overlays and Fig 2 shows that in the Fig 3 overlay the algorithms have highlighted both dislocations and grain boundaries. It will also be noticed that some grain boundaries faintly visible in the Fig 2 image, such as those in the lower left corner region labelled 12, do not appear in the Fig 3 overlay because their relative PL intensity was not below threshold. Thresholding allows wafers to be graded according to the 'intensity' of a given defect type, which may for example be indicative of the extent of metal decoration. From these or other overlays one can calculate one or more metrics, such as an area fraction or relative density or intensity, representative of the occurrence of the selected feature(s) in the sample, which can be used to grade or sort wafers.

[0069] Other significant features of interest to cell manufacturers include regions of high impurity concentration that, because of reduced carrier lifetime, typically appear in PL images as extensive dark areas. For muiticrystalline or other cast silicon wafers, the occurrence of high impurity regions generally depends on the position within an ingot from which the wafers were cut. Typically, silicon that crystallised in regions adjacent to the crucible walls has a much higher concentration of impurities, such as iron, than silicon that crystallised in the interior of an ingot. Consequently, and with reference to Fig 1 , PL images of wafers cut from an 'edge' brick 4E or a 'corner' brick 4C typically show low intensity regions along one edge and two adjacent edges respectively, while PL images cut from a 'middle' brick 4M are typically clear of such features. Impurity levels are generally also high in wafers cut from close to the bottom and top of a brick. By way of illustration, Fig 5.1 shows a PL image of a wafer cut from the bottom of an edge brick, while Fig 5.2 shows a PL image of a wafer cut from part way up the same brick. Both images show a dark band 13 along one edge indicative of a high impurity region, while Fig 5.1 also shows a contrast inversion compared to Fig 5.2 along dislocations and grain boundaries (i.e. features are bright instead of dark); such contrast inversions are typically seen in PL images of wafers cut from the top or bottom sections of bricks, and are caused by internal gettering of impurities which is only effective in impurity -rich regions. This contrast inversion is one means by which top or bottom wafers (high impurity levels) can be distinguished from wafers with low impurity levels, bearing in mind that both types of wafer can exhibit substantially uniform intensity across a PL image. Another means is to normalise the PL images with measured carrier lifetime. Wafers cut from the top and bottom of a brick can generally be distinguished from each other under PL imaging because the former tend to have much higher dislocation densities, as revealed by the number of contrast inversion features.

[0070] Turning now to specific examples of wafer grading schemes, reference is made to Fig 6 showing a grading system flowchart in accordance with a preferred embodiment of the present invention. The process begins with an imaging step 14, where one or more PL

(photoluminescence) images of a wafer are acquired, followed by an optional image conditioning step 16 where the images may be corrected for known artefacts e.g. flat field correction, or high pass filtered to suppress long range intensity variations. The images are then processed in an image processing step 18, for example using a line detection algorithm to highlight features of interest, and in step 20 one or more defect-related parameters of significance for PV cell performance are calculated. This results, in step 22, in quantification of the key PL defects. A non-PL-based analysis step 24 is also conducted, where one or more additional wafer properties such as resistivity, thickness or effective lifetime are measured at one or more points and fed into the process. From the combination of the resultant PL analysis 22 and non-PL-based analysis 24, a grade is calculated and applied to the wafer in a grading step 26. Wafer properties measured in the non-PL-based analysis step, e.g. resistivity, lifetime or thickness, may also be fed into the image processing step as indicated by the dotted arrow 27. Graded wafers may then pass to a PV cell line 28 immediately or, as discussed in more detail below, they may be sorted 30 into a reduced number of classifications or bins prior to entry into the PV cell line. Optional steps in Fig 6 are indicated by dotted boxes or arrows.

[0071] In one example grading system, explained with reference to Table 1, grading is based on three measurement outcomes, namely:

i. impure area fraction as extracted from PL imaging data

ii. dislocation area fraction as extracted from PL imaging data, and

iii. doping level as extracted from resistivity data.

Table 1

[0072] Iii this example the 'impure area fraction' metric is calculated from the area fraction in a PL image occupied by extensive 'dark' regions, such as the edge region 13 in Fig 5.2, indicative of high impurity levels; a lower figure obviously indicates higher quality. Generally speaking, grade A wafers (0 to 1% impure fraction) can be expected to come from 'middle' bricks, while grade B and C wafers can be expected to come from both 'edge' and 'corner' bricks, as defined above in discussing Fig 1. If wafers are sourced from upgraded metallurgical grade (UMG) silicon, then wafers cut from close to or within the 'transition' region (where the p-type and n-type dopants cancel each other out to produce effectively undoped silicon) will often be in grades B, C or D. Wafers cut from the top or bottom of bricks typically have high levels of impurities throughout, and will generally be in grade E.

[0073] Referring again to the example grading system of Table 1, the 'dislocation' metric is calculated from the area fraction in a PL image occupied by features identified to be dislocations; again, a lower figure indicates better quality. The example grading system also has four grades for doping/resistivity. The impact of doping on cell performance is complex. Generally higher doping results in higher open circuit voltage but in reduced short circuit current. The optimum doping depends critically on the cell design and cell process and the efficiency range that is achieved in that cell process. An optimum doping range can be defined for a specific cell line, for which cell efficiency is maximised, and deviations from that optimum doping captured in our grading scheme.

[0074] Other metrics such as the degree of multicrystallinity, or thickness or thickness variation data (used as a correction factor to account for the volume of silicon in a wafer) can be used to refine the example grading process, or as the basis for other grading processes. As per Table 1 above, each key metric has a finite number of grades or categories (e.g. A to E for impure fraction) that are considered to be important - the choice of the number of these is limited at the upper end by practical factors such as the number of sorting bins (if physically binned) that can reasonably be afforded, and at the lower end by ensuring wafers in each category have sufficiently differentiated properties. Also of consideration is that the range of values in each category should be substantially larger than the error of measurement - it would be of little use if the mean values in neighbouring categories were separated by less than the measurement error for example.

[0075] The above described grading scheme example leads to as many as 120 potential grades, based on the combination of five impurity categories, six dislocation categories and four doping/resistivity categories. Although this potential is somewhat limited by measurement realities such as the increased difficulty of reliably detecting dislocations in high impurity 'top' and 'bottom' wafers because of the contrast inversion (see Fig 5.1), some rationalisation of the number of grades, and sorting of the resulting grades into classifications or bins, is desirable for reasons of practicality. Advantageously, the rationalisation procedure will be chosen such that the limits (borders) to each grade are optimised to minimise the efficiency distribution within bins. By way of example, we will describe a procedure for converting the wafer grading scheme of Table 1 to a set of 28 grades as shown in Figure 7.

[0076] Step 1 : Distribute wafers into grades A-F based on the impure fraction metric, where the highest impure fraction wafers (top or bottom wafers) are divided between grades E and F depending on whether the impurity levels are below or above a predetermined threshold; the former can be expected to have somewhat better quality for PV purposes as the impurities can be mostly gettered.

[0077] Step 2: Distribute grade A wafers into sub-grades Al to A6 based on categories 1 to 6 of the dislocation metric, and likewise for grades B, C and D. Grade E and F wafers are only distributed into sub-grades El Fl or E6/F6, depending on whether they are bottom wafers (fewer dislocations therefore better quality) or top wafers (more dislocations).

[0078] Step 3: Shift wafers into neighbouring sub-grades by resistivity measurement, i.e. doping. This step does not apply to grade E or F wafers, and wafers cannot cross impure fraction grades; e.g. they cannot shift from A6 to Bl . The effect of this step is to move wafers into higher or lower quality sub-grades if they have favourable or unfavourable

resistivity/doping for the relevant cell design and cell process.

[0079] The resultant grades are shown in Figure 7. The total number of grades in this example is 28, comprising six grades each for A, B, C and D type wafers, and two grades each for E and F type wafers.

[0080] Grading schemes of greater or lesser complexity are also within the scope of the present invention. A particularly simple grading scheme has only two grades, e.g. 'pass' and 'reject', based for example on the absence or presence of cracks or an unacceptable impure area fraction. Another simple grading scheme may have three grades, e.g. 'high performance cell line', 'standard cell line' and 'reject'. In these simple schemes the grading is essentially indicative of the suitability of a wafer for a given cell manufacturing process, For schemes with a larger number of grades, the limits or borders for each of the grades are preferably set such that: (a) within most or all grades there is roughly the same number of wafers; and (b) within each grade the wafers when processed into cells on a specific cell line will give the minimum spread of IV results.

[0081] There are a number of reasons to grade wafers including assigning an economic value based on the defects and other characteristics of the wafer. A cell manufacturer may know that certain grades of wafers have certain cell performance when processed through their lines, providing different economic value for different grades.

[0082] Similarly each grade of wafers can be processed with different process conditions, possibly on different lines, where each set of process conditions is chosen to maximise the cell performance for that wafer grade. In a conventional arrangement on the other hand, all wafers are generally processed with the same conditions, which provides a sub-optimal outcome.

[0083] Another benefit of grading wafers is inventory management, where wafers can be processed to meet a defined IV (current-voltage) outcome to fulfil a specific customer order for cells of a certain characteristic. As will be clear to a person skilled in the art, maintaining an inventory of unprocessed but graded wafers is much cheaper and more efficient than keeping an inventory of various fully processed cells with differing IV characteristics. Using such a graded inventory gives maximum flexibility and reduces costs to the cell manufacturer. Alternatively, a wafer manufacturer can maintain graded populations of wafers for supply to a cell manufacturer on request. Keeping inventory in wafers is cheaper than keeping inventory in cells or modules.

[0084] Yet another benefit of grading wafers is to allow wafer suppliers to supply good quality wafers, or to market their higher value wafers. Yet another benefit of grading wafers is to enable the identification of wafers with specific properties for advanced cell process designs and/or cell lines. One example is selective emitter cell concepts and lines, where there is often very little gettering capacity inherent in the process, meaning it is especially advantageous to select wafers with very few impurities. Still another benefit of grading wafers is the use of continual manufacturing improvement. By grading wafers and understanding the impact of material properties on cell performance, it is much easier both to modify the cell manufacturing line to improve performance of cells from a specific wafer grade, and also to understand and improve the impact of the cell line on cell performance. Again, this would be virtually impossible if an ungraded, continually varying supply of wafers were supplied to the cell manufacturing line. It will be appreciated that there are many other uses of the wafer grading system described in this specification.

[0085] Many of the suggested applications of our wafer grading system include sorting the wafers, either physical or virtually, into classifications or bins. A physical bin can be a collection of wafers of the same grade, or a known mix of grades. Once a production line has been 'calibrated', i.e. the relationship between each grade or classification and the cell performance is known, then (a) the number of classifications can be reduced to a more practical level, and (b) the sorting can be used as per whatever economic model(s) is desired.

[0086] The resultant grading/sorting system can provide significant short term and long term benefits to cell manufacturers by allowing them to optimise the cell lines. This can be done by either using empirical or semi-empirical data following the above discussed 'calibration' of the cell lines. In some instances, however, no such calibration would be required and there would be a clear analytical relationship between the measured properties and the resultant IV performance of the cells produced from the respective semiconductor material.

[0087] Fig 8 shows a graphical representation of a sorting system in accordance with a preferred embodiment of the present invention, where certain grades are grouped into classifications or bins for a PV cell line. A selection of wafer grades is plotted against the range of IV characteristics of cells made from wafers of those grades on that cell line, and it can be seen that several grades of wafers provide PV cells which have quite similar IV characteristics. In this regard it should be noted that Fig 8 is used purely for illustrative purposes and should not be taken as defining that certain grades will provide certain IV characteristics.

[0088] In the illustrative example shown, for instance, grade A4 wafers are known to produce cells with IV characteristics similar to cells made from grade B3, C2 and Dl wafers. Accordingly, these four grades (A4, B3, C2, Dl) can all be sorted into a single classification or bin, for instance bin 4. A cell manufacturer may simply select from that bin and know that the resultant cells will have relatively consistent IV performance. In preferred embodiments the grades of wafers are chosen for sorting into classifications based on a requirement that all wafers in a respective classification will produce photovoltaic cells having an efficiency variance of -less than ¾, preferably less than ½, and more preferably less than 1/3 of the efficiency variance of photovoltaic cells produced from an ungraded and unsorted population of wafers. Alternatively, a wafer manufacturer can produce wafers having a grade of A4, B3, C2, Dl and market them to a cell manufacturer as being of equivalent standard.

[0089] It will be understood that the aforementioned grading and sorting system can provide an international standard against which all wafers can be graded. This permits wafer manufacturers maximum flexibility and certainty when marketing their product and more importantly allows cell manufactures to tailor their source material based on the desired IV outcome for their cells. If used throughout the industry, this grading standard will have significant industry-wide benefits.

[0090] We turn now to description of a wafer sorting tool that may for example be used to sort wafers at the end of a wafer manufacture line or at the beginning of a line for

manufacturing devices such as PV cells from the wafers. As illustrated schematically in Figs 9A (side view) and 9B (plan view) a wafer sorting tool 46 comprises a measurement section 48, a number of destination bins 50A to 50D, a transport mechanism for conveying wafers 32 into, through and out of the measurement section, a control computer 52, and a transfer mechanism 54 for transferring wafers to the destination bins as directed by the computer, for example using platens or suction cups. Although the transport mechanism is illustrated as three separate transport belts 36A, 36B and 36C or the like (e.g. rollers), in other embodiments the transport mechanism may comprise more or fewer belts or the like. The transport mechanism 36B for conveying wafers through the measurement section will generally be designed to meet the requirements of the various measurement systems within the measurement section 48 and, as illustrated in Fig 10, may for example include separate sections 56 for bringing wafers to a stop momentarily and gaps 58 for allowing access to both sides of wafers, e.g. for thickness or IR transmission measurements.

[0091 ] The measurement section 48 contains one or more systems for analysing

semiconductor wafers, including for example systems for acquiring photoluminescence or optical reflection images of a wafer, and systems for measuring one or more of resistivity, effective lifetime, IR transmission or thickness at one or more points across a wafer. In certain embodiments the measurement section includes at least a photoluminescence imaging system and a system for measuring wafer resistivity. If wafers are moved across a sensor head, such as a resistivity coil, then data can be acquired at several sampling points or averaged across the sampled area. In other embodiments the measurement section includes a photoluminescence imaging system and a system for measuring effective lifetime, such as quasi-steady state photoconductance or microwave detected photoconductance decay. In certain embodiments the measurement section also includes a thickness monitor, for example based on capacitance measurements, for measuring wafer thickness. The photoluminescence imaging system may for example acquire two-dimensional images in an area imaging or line scanning fashion. The various measurement systems may be housed together in a single unit or spaced apart.

[0092] Systems for measuring one or more of resistivity, effective lifetime, IR transmission or thickness can be adapted to obtain data at one or more points across a wafer, which may for example be scattered, or on a raster grid, or in one or more lines if wafers are moved across one or more sensor heads. The sampling points may be contiguous, e.g. in the form of a linescan. For accuracy of the analysis and ultimately of the grading or sorting processes, it is preferable for the various data sets to be in spatial registration so that, for example, resistivity and thickness data from the same point on a wafer are used to normalise the PL count at that point. In some cases the data sets will be acquired in a spatially registered manner, for example a set of thickness data measured at points within an area imaged by a photoluminescence imaging system, or sets of thickness and resistivity data measured at the same points. In other cases, for example where sets of thickness and resistivity data are measured at different points, e.g. along two or more lines or along one line with different spacings, the control computer 52 can bring the data sets into spatial registration by interpolation or extrapolation of at least one of the data sets.

[0093] Referring back to Figs 9A and 9B, the computer will in general terms have program code suitable for controlling the various measurement systems and transport mechanisms, for processing the measured data to assign grades to the sample wafers, and for directing the transfer mechanism 54 to transfer each wafer to the appropriate destination bin, via wired or wireless connections 60 that are shown schematically in Fig 9A only. As indicated by the arrow 62 the computer may also obtain data measured at the brick stage, such as

photoluminescence, lifetime or resistivity data, to feed into the wafer grading process. ^' [0094] Image processing and analysis methods such as those described above for identifying recombination active defects that are line shaped or in dense clusters, e.g. obtaining the overlays of Fig 3 and 4 respectively from the PL image of Fig 2, are primarily concerned with obtaining metrics for the extent of recombination active defects in wafers without necessarily distinguishing between types of defects, e.g. dislocations, grain boundaries, impure regions and cracks. Other analysis methods may aim to distinguish between defect types in one or more wafers, then quantify the density of each defect in the wafers for grading or sorting purposes and/or track the defect density or recombination activity as the wafer progress along a PV cell line.

[0095] Of particular interest is differentiating between grain boundaries and dislocations; this is rarely a problem in monocrystalline silicon wafers given the absence of grain boundaries, but sophisticated methods are often required for multicrystalline silicon wafers. Cast

monocrystalline silicon, also referred to as 'seeded casting' silicon, which is currently thought to be a viable alternative to conventional CZ silicon for PV applications, occupies a middle ground. Often, cast monocrystalline silicon wafers are largely monbcrystalline, with only small sections consisting of multicrystalline material. The optical reflection image of a cast monocrystalline wafer shown in Fig 1 1 is featureless, indicating an absence of multicrystalline material. However this wafer still has extensive recombination active dislocation networks as clearly shown by the dark line features in the PL image of Fig 12. With no ambiguity between dislocations and grain boundaries in this case, it is relatively straightforward for an edge detection algorithm to identify and quantify the dislocations. More sophisticated algorithms may only be required to analyse multicrystalline sections, reducing the overall computational load and analysis time. In certain embodiments cast monocrystalline wafers are graded or sorted according to the severity of dislocations, quantified for example as average dislocation density across a wafer, so that wafers with dislocation density above a threshold can be directed to an annealing station before entering the PV cell line, or directed to an alternate PV cell line with an annealing station. In other embodiments cast monocrystalline wafers are graded or sorted according to the area fraction of multicrystalline material, so that they can be directed to different texturing processes.

[0096] For samples such as multicrystalline wafers where there is ambiguity between different defect types, it will sometimes be beneficial to acquire and compare multiple images. In one example, it has been shown in published PCT patent application No WO 1 1/079353 Al that some recombination active defects appear much sharper, and therefore easier to identify, in PL images acquired with much higher illumination intensities, e.g. 100 or 1000 Suns instead of 1 Sun, implying much higher injection levels. More generally, comparing PL images acquired with a range of injection levels can aid in distinguishing between defect types. In another example, it has been suggested in the abovementioned published PCT patent application No WO 2009/121 133 Al that comparing PL and optical images can be useful in this context, because optical images reveal grain structure but not features such as dislocations (unless the sample has been chemically etched) or impurities. A system for acquiring PL and optical reflection images is shown in schematic side view in Fig 13, comprising: a light source 64 and a camera 66 for obtaining a reflection image of a wafer 32; a source 68 of sufficiently high intensity to generate photoluminescence 70 from the wafer material that can be imaged with a second camera 72; and a computer 74 for processing and comparing the reflection and PL images. Other optical components such as lenses and filters will also be present as required, as described for example in the abovementioned published PCT patent application No WO

2007/041758 Al. As noted previously it is possible to inspect stationary or moving wafers with appropriately designed systems. The PL and reflection imaging components can be co-located as shown in Fig 13 or arranged separately. We note that both types of images could be acquired with one source and one camera (e.g. an 805 nm laser and a Si CCD camera, for silicon wafers) with some additional components such as moveable neutral density or cut-off filters, but this would require the images to be acquired sequentially, increasing the inspection time. Another alternative system includes a single light source of sufficiently high intensity to generate photoluminescence from the wafer material, and two cameras with filters as required, suitable for acquiring PL and reflection images respectively. Photoluminescence and optical images can both be analysed by image processing algorithms adapted to calculate a variety of metrics related to grain structure, such as average grain size, grain size distribution, number of grains in a wafer, total length of grain boundaries, for comparison with dislocation patterns/structure.

[0097] The Fig 13 system does however have a limitation in that because the extent of discernible grain structure in a multicrystalline silicon wafer depends on the illumination and viewing angles, a single reflection image may not reveal the entire grain structure for comparison with a PL image. Because the appearance of individual grains in multicrystalline silicon depends on their surface texture, adjacent grains with similar textiire can be difficult to discern from a single perspective, i.e. combination of illumination and viewing angles. The optical imaging can be improved in several ways, for example using multiple sources or cameras to acquire several reflection images (e.g. up to 20 or more) from two or more perspectives or wavelengths, e.g. using multiple wavelengths or rotating the sample or moving the illumination source or camera between exposures. However the sequential acquisition of multiple images increases the inspection time and the registration of multiple images for comparative purposes requires image processing resources. These disadvantages can be avoided if multiple reflection images are acquired simultaneously using a colour-sensitive camera and two or more sources emitting light of different colours. By way of example, Fig 14 shows in schematic side view an optical imaging system comprising red, green and blue LEDs 64R, 64G and 64B that illuminate a multicrystalline silicon wafer 32 from different angles, imaging optics 76, a colour line camera 78 (typically with RGB filters deposited directly on alternating pixels as shown in Fig 14 A) for acquiring images of the wafer in red, green and blue light as it passes through the system on a transport belt 36 or similar transport mechanism, and a computer 74 for analysing and comparing the three images to determine the grain structure in the wafer. It will be appreciated that PL imaging components (e.g. a high intensity source, line camera, optics and filters) could be included in the same system or in a separate system. It will also be appreciated that a colour area camera could be used instead of a line camera, e.g. for inspecting stationary samples, or even for inspecting samples in motion if the optical sources emit pulses sufficiently short for there to be minimal image blurring. It is convenient to use RGB cameras because of their commercial availability, but any combination of colour-sensitive camera and multiple sources of appropriate wavelength could be used instead.

[0098] Although the present invention has been described with particular reference to certain preferred embodiments thereof, variations and modifications of the present invention can be effected within the spirit and scope of the following claims.