Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
WAFER-LEVEL CHIP SCALE PACKAGE (CSP) STRUCTURE AND PREPARATION METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2019/120309
Kind Code:
A1
Abstract:
The present invention relates to a wafer-level chip scale package (CSP) structure and a preparation method therefor. The wafer-level CSP structure comprises a chip. A light-exiting surface of the chip is provided with a first-concentration fluorescent layer to form a package A, and less than 10% of the area of the light-exiting surface of the chip is covered by the first-concentration fluorescent layer. The top surface and side surfaces of the package A are further provided with a translucent or transparent second-concentration fluorescent layer to form a package B. The concentration of fluorescent powder in the first-concentration fluorescent layer is recorded as w1, the concentration of fluorescent powder in the second-concentration fluorescent layer is recorded as w2, and w1>w2. The first-concentration fluorescent layer and the second-concentration fluorescent layer are formed by spraying fluorescent powder twice successively, thereby facilitating achieving a target value in process production, reducing the process difficulty, and improving the yield of devices. The wafer-level CSP structure of the present invention can improve the heat dissipation performance of light emitting chips, reduce the preparation costs of devices, and improve the reliability and uniformity of the devices.

More Like This:
JP5175488LED package with multi-layer reflective surface structure
JP7197686Light-emitting element, manufacturing method thereof, and display device provided with light-emitting element
WO/2003/051431IMPROVEMENTS IN AND RELATING TO A MEDICAMENT INJECTION APPARATUS
Inventors:
WANG SHUCHANG (CN)
FAN AIJIE (CN)
SUN ZHIJIANG (CN)
Application Number:
PCT/CN2018/123064
Publication Date:
June 27, 2019
Filing Date:
December 24, 2018
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
DURA CHIP NANTONG LTD (CN)
International Classes:
H01L33/48; H01L33/50; H01L33/52
Domestic Patent References:
WO2009039801A12009-04-02
Foreign References:
CN204497271U2015-07-22
CN102593327A2012-07-18
US20150008464A12015-01-08
Download PDF:
View/Download PDF      PDF Help



 
Previous Patent: METHOD AND SYSTEM FOR PREDICTING ROAD CONDITION, AND MOBILE TERMINAL

Next Patent: BASE EDITING SYSTEM AND METHOD BASED ON CPF1 PROTEIN