Title:
WAFER LEVEL SYSTEM PACKAGING METHOD AND PACKAGING STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2020/047976
Kind Code:
A1
Abstract:
Disclosed are a wafer level system packaging method and packaging structure, the wafer level system packaging method comprising: forming a bonding structure, wherein the bonding structure comprises a device wafer (10) and a plurality of chips (20) bonded to the device wafer (10), wherein a chip (10) to be shielded in the plurality of chips (20) is a first chip (13), and the number of first chips (13) is one or more; forming a packaging layer (12) covering the plurality of chips (10); forming, in the packaging layer (12), a groove (14) surrounding each first chip (13); and forming a conductive material in the groove (14) and a conductive material on a surface of the packaging layer (12) above the first chip (13), wherein the conductive material in the groove (14) is a conductive side wall (151), and the conductive material on the surface of the packaging layer (12) above the first chip (13) is a conductive layer (152) for connecting to the conductive side wall (151) so as to constitute a shielding shell (15). According to the wafer level system packaging method and packaging structure, the volume and thickness of the formed packaging structure can be reduced.
Inventors:
LUO HAILONG (CN)
DROWLEY CLIFFORD IAN (CN)
DROWLEY CLIFFORD IAN (CN)
Application Number:
PCT/CN2018/113108
Publication Date:
March 12, 2020
Filing Date:
October 31, 2018
Export Citation:
Assignee:
NINGBO SEMICONDUCTOR INT CORP (CN)
International Classes:
H01L23/552
Foreign References:
CN107104094A | 2017-08-29 | |||
CN103035591A | 2013-04-10 | |||
CN107481977A | 2017-12-15 | |||
CN107248509A | 2017-10-13 | |||
CN106898580A | 2017-06-27 | |||
US20170330839A1 | 2017-11-16 |
Attorney, Agent or Firm:
INTEBRIGHT LLP (CN)
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