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Patent Searching and Data


Title:
WIRING STRUCTURE, METHOD FOR PRODUCING SAME, AND IMAGING DEVICE
Document Type and Number:
WIPO Patent Application WO/2022/014400
Kind Code:
A1
Abstract:
The present invention provides a wiring structure which is suitable for reduction of the wiring capacitance. This semiconductor device comprises: a wiring layer which comprises a plurality of wiring lines that extend in a first direction; a first insulating film which is superposed on the wiring layer and comprises a void that is present in a gap region which is sandwiched between a plurality of wiring lines that are adjacent to each other in a second direction; and a second insulating film which is arranged between a plurality of wiring lines and the first insulating film. Each wiring line comprises: a metal film which is formed of a conductive material that contains a first metal; and a barrier metal layer which partially covers the periphery of the metal film in a cross-section that is perpendicular to the first direction, while being formed of a material containing a second metal that suppresses diffusion of the first metal. The second insulating film is arranged so as to cover a part of the metal film, and contains an insulating material that suppresses diffusion of the first metal.

Inventors:
SEJIMA KOICHI (JP)
FUKATANI TAKASHI (JP)
NISHIO KENYA (JP)
HANEDA MASAKI (JP)
FUJII NOBUTOSHI (JP)
SAITO SUGURU (JP)
Application Number:
PCT/JP2021/025405
Publication Date:
January 20, 2022
Filing Date:
July 06, 2021
Export Citation:
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Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L21/82; H01L21/3205; H01L21/768; H01L21/822; H01L21/8234; H01L23/522; H01L23/532; H01L27/00; H01L27/04; H01L27/06; H01L27/088; H01L27/146; H04N5/369
Domestic Patent References:
WO2018186197A12018-10-11
Foreign References:
JP2009188250A2009-08-20
JP2009290240A2009-12-10
JP2018507546A2018-03-15
US10438843B12019-10-08
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
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