Title:
WRITE OPERATION CIRCUIT, SEMICONDUCTOR MEMORY, AND WRITE OPERATION METHOD
Document Type and Number:
WIPO Patent Application WO/2021/077783
Kind Code:
A1
Abstract:
At least provided by the embodiments of the present application is a write operation circuit, comprising: a serial-to-parallel conversion circuit, which is used for performing serial-to-parallel conversion on first DBI data of a DBI port so as to generate second DBI data for transmission by a DBI signal line, and generating input data of a data buffer module according to the second DBI data and input data of a DQ port; the data buffer module, which is used for determining according to the input data of the data buffer module whether to turn over a global bus; DBI decoding modules, which are used for decoding global bus data according to the second DBI data and writing the decoded data into a storage block, the decoding comprising determining whether to turn over the global bus data; and a pre-charging module, which is connected to a pre-charging signal line and used for configuring the initial state of the global bus as high. The technical solution of the embodiments of the present application can, under a Precharge pull-up architecture, achieve a reduction in the number of turnovers of a global bus to thereby greatly compress current and reduce power consumption.
Inventors:
ZHANG LIANG (CN)
Application Number:
PCT/CN2020/097504
Publication Date:
April 29, 2021
Filing Date:
June 22, 2020
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/409
Foreign References:
| CN210575117U | 2020-05-19 | |||
| CN109582507A | 2019-04-05 | |||
| CN107545918A | 2018-01-05 | |||
| CN104681085A | 2015-06-03 | |||
| CN108872837A | 2018-11-23 | |||
| US20100042889A1 | 2010-02-18 | |||
| CN201911021460A | 2019-10-25 |
Other References:
See also references of EP 3896694A4
Attorney, Agent or Firm:
CHANG TSI & PARTNERS (CN)
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