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WO/2006/081096A2 |
A circuit has a phase adjustment circuit to generate an adjusted clock signal by adjusting a first clock signal in accordance with a control signal. A multiplexer receives input data signals on a plurality of first data lines and outputs...
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WO/2006/074870A1 |
The invention relates to a controller for generation of control signals (evload_o, odload_o, st_chgclk_o, clk_o, clk_or_fiford_i), synchronous with a continuously supplied clock signal (clk_hr_i) for a device (1) for control synchronousl...
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WO/2005/107080A2 |
A serializer and a de-serializer are disclosed and shown operating singly or as a pair. The invention operates independently from any outside system reference clock. The inventive system provides an internal bit clock that serializes the...
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WO/2005/101773A1 |
[PROBLEMS] To realize a highly-reliable, stable digital data transmission without the need of reference clock and shake-hand operation. [MEANS FOR SOLVING PROBLEMS] A digital data transmission method for alternatively and periodically tr...
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WO/2005/091543A1 |
A bi-directional serializes/de-serializes is disclosed using a single bi-directional data line and a single bi-directional clock line. Gated buffers are controlled to operate either sending or receiving data, and a phase locked loop prov...
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WO/2005/091544A1 |
A bi-directional serializer/de-serializer is disclosed using a single bi-directional data line and a single bi-directional clock line. Gated buffers are controlled to operate either sending or receiving data, and a phase locked loop prov...
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WO/2005/055432A1 |
A reconfigurable data conversion device (10) is described that allows for all of its component parts needed for manipulating data (12), converting the data into serial format (14) and into an optical signal (16,18) to be provided on a si...
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WO/2005/029869A1 |
There is provided a system for forming a digital multimedia link, comprising transmitter means comprising downstream framer means, receiver means comprising downstream deframer means, serializer means, and deserializer means, wherein at ...
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WO/2005/022593A2 |
A high-speed communication interface manages a parallel bus having N bus lines. N+1 communication lines are established. A maintenance operation is performed on one of the N+1 communication lines, while N of the N+1 communication lines i...
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WO/2005/018094A1 |
A semiconductor integrated circuit device (1) includes: a transistor switch (SWA) for electrically connecting and disconnecting output of a flip-flop (FF64) of a shift register (SR1) and input of a flip-flop (FF65) of a shift register (S...
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WO/2004/093377A1 |
A signal transmitting apparatus includes a sending part and a receiving part. The sending part converts each width of a plurality of digital input signals into a voltage in accordance with a predetermined weight, generates a send signal ...
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WO/2004/088851A1 |
A signal transmission method and a signal transmission device capable of easily transmitting a signal with a small number of signal lines. A data signal of time slot count N+&agr with bit count N is longitudinal-lateral converted into a ...
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WO/2004/038994A1 |
A device for transferring data signals between a first clock domain and a second clock domain comprises a serial memory element and a parallel memory element which are coupled. The serial memory element comprises at least one extra memor...
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WO/2003/088500A1 |
A technique includes providing a first clock signal to a parallel-to-serial data conversion circuit (54) and providing a second clock signal to a memory (52) storing data for conversion by the conversion circuit. One of the first and sec...
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WO/2003/069868A1 |
A randomizing unit (101) makes the number of 1 and the number of 0 of the data identical. A coding unit (102) performs coding of the data in which the number of 1 and the number of 0 have been made identical. An HS-DSCH modulation spread...
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WO/2003/063369A2 |
A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial...
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WO/2003/046391A2 |
A hybrid serial/parallel bus interface for a base station has a data block demultiplexing device (40). The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality...
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WO/2003/046738A1 |
A hybrid serial/parallel bus interface method for a base station has a data block demultiplexing device (40). The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a pl...
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WO/2003/046737A1 |
A hybrid serial/parallel bus interface for a user equipment (UE) has a data block demultiplexing device (40). The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a pl...
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WO/2003/047114A1 |
A hybrid serial&sol parallel bus interface has a data block demultiplexing device (40). The data block demultiplexing device (40) has an input configured to receive a data block and demultiplexes the data block into a plurality of nibble...
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WO/2003/047113A1 |
A hybrid serial&sol parallel bus interface method for a user equipment (UE) has a data block demultiplexing device (40). The data block demultiplexing device (40) has an input configured to receive a data block and demultiplexes the data...
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WO/2003/028221A1 |
A high−speed and high−accuracy parallel&sol serial converter. A PLL circuit (50) inputs a clock CLK, locks it, and supplies it to components of an apparatus. The PLL circuit (50) controls a 16−tap ring oscillator (60) and shifts th...
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WO2001069837A9 |
A programmable logic device ("PLD") is augmented with programmable clock data recover ("CDR") circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PL...
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WO/2003/003713A1 |
A fully digital pulse width modulator substantially doubles resolution in a laser printer by outputting data to the laser on both the rising and falling edges of the clock cycle. A counter and the clock itself are used to select input to...
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WO2001095497A9 |
The present invention provides a system and method for high speed digital information transmission that pushes the underlying technology to its upper limits. The system and method operate using an input clock with a frequency that also h...
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WO/2002/056189A1 |
The invention relates to a data reception circuit for the reception of a serial input data stream with a high data transmission rate. The data reception circuit comprises a data stream division circuit (4) for subdividing the serial inpu...
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WO/2002/043149A1 |
A semiconductor chip (1) comprises function blocks (2¿-1?, 2¿-1?) including serial/parallel converting sections (4¿-1?, 4¿-2?) for converting serial data to parallel data and vice versa. Only serial data is inputted/outputted into/fr...
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WO/2002/023737A1 |
A demultiplexer apparatus includes a plurality of series-connected integrators (10). The plurality of integrators receive serial binary data. A current-stage one of the plurality of integrators converts the serial binary data into a mult...
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WO/2001/095626A2 |
An HFC return path system for digital communication signals using a sampled RF word interface to headend demodulators, provides higher performance equipment at an equivalent of lower cost and more flexible and efficient interfacing and t...
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WO1999048260A9 |
A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same int...
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WO/2001/004673A1 |
An apparatus for converting an input optical serial data pulse stream (223) into output optical parallel pulse streams comprises a waveguide (224) that provides optical parallel pulse streams resulting from second-harmonic radiation gene...
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WO/2000/070768A1 |
An apparatus for decoding a serial datastream of channel words into a datastream of information words is provided. The apparatus comprises an input terminal (10) for receiving the serial data stream of channel words, a serial-parallel co...
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WO2000036780A9 |
A device (40) for converting at least four parallel data streams on respective input data (P0-P3) into one serial data strea m on a fiber optic data line (18). The device (40) includes a first multiplexer (42) for multiplexing at least t...
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WO/2000/064056A1 |
A circuit arrangement is described for converting a parallel data stream into a serial data stream and for intermediate storage and clocked supply of the data stream, which is characterized in that a first shift register (1) is provided ...
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WO/2000/056003A1 |
The invention relates to a monitoring method and monitoring arrangement, which receives a parallel-mode signal transferred to the arrangement by using a clock signal. The monitoring arrangement comprises a counter (24) counting clock sig...
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WO/2000/025431A1 |
A serial-to-parallel/parallel-to-serial conversion engine that provides a bi-directional interface between a serial and a parallel TDM highway. The serial-to-parallel data conversion device includes a serial data input interface that rec...
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WO/2000/013320A1 |
A deserializing section (130) samples serial data DA1 generated b y serializing parallel data and including a first data stream inputted subsequently to a synchronizing period and containing one or more unit data streams (00XXX...XXX) ea...
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WO/2000/000653A1 |
A method for producing new superplastic alloys by inducing in an alloy the formation of precipitates having a sufficient size and homogeneous distribution that a suffiently refined grain structure to produce superplasticity is obtained a...
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WO/1999/048215A1 |
A high-speed switching circuit which operates at speed exceeding 20 GHz. High-speed light-activated switches (PSW1, PSW2) controlled by light are connected with a plurality of input terminals (D¿in1?, D¿in2?), and their outputs are con...
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WO/1999/048180A2 |
A selective bi-directional parallel-to-series conversion module (2) for use with a digital camera (4) and a modem (6), and a method for transmitting and processing image data and command signals. The binary digital output from a digital ...
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WO/1999/013586A1 |
A system and method for converting data between a multi-bit time division multiplexed bus and a faster single-bit TDM bus, wherein each TDM bus communicates data by means of frames, each frame comprising a fixed number of slots and each ...
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WO/1998/027678A1 |
The invention relates to demultiplexing of high frequency data signals. The data signal is first frequency divided before extracting a clock signal, which is necessary to sample the data signal to provide plural, parallel data channels. ...
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WO/1997/049186A1 |
The invention relates to fast serial-parallel and parallel-serial converters, and in them included frequency dividers. The serial-parallel converter comprises a shift register (51), an output register (52) and a frequency divider (40). T...
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WO/1997/048056A1 |
A system and method for sending multiple data signals over a serial link comprises an embedding unit and a removing unit coupled by a serial line. The embedding unit preferably receives a plurality of data streams, encodes the data strea...
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WO/1997/031316A1 |
A demultiplexer (10) includes an input stage (12) that receives a serial data stream having a plurality of m-bit sections at a first clock rate. The input stage converts successive n-bit portions of each m-bit section into a first n-bit ...
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WO/1996/021974A1 |
The Serial Peripheral Interface (SPI) is designed to drive multiple SPI peripherals via a simple serial connection. The number of devices controlled is easily expanded without modifying the looming or main board interface. Peripheral out...
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WO/1996/021897A1 |
A data transmission system, in which data streams shall be transmitted with great speed between a sending clock domain and a receiving clock domain, which operate with mutually different clock speeds, includes two system part circuits (2...
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WO/1996/005658A1 |
A serial/parallel converter is proposed which comprises a shift register arrangement (12', 12'' to 12n) and an output register arrangement (13', 13'' to 13n), each of which comprises n storage devices (12', 12'' to 12n; 13', 13'' to 13n)...
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WO/1995/002951A1 |
A time division switching matrix capable of effecting rate conversion comprises a plurality of serial inputs for connection to respective serial input links, each capable of carrying time division multiplexed PCM channels, a plurality of...
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WO/1994/012926A1 |
A network extender (24) for a computer network including multiple computers (10) interconnected with a shared, common memory (18, 20). A computer system interface (12) interconnects the multiple computers (10) and control data flow betwe...
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