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Title:
CARRIER, CARRIER MANUFACTURING METHOD, CARRIER EVALUATION METHOD, AND SEMICONDUCTOR WAFER POLISHING METHOD
Document Type and Number:
Japanese Patent JP2019186490
Kind Code:
A
Abstract:
To provide a carrier capable of obtaining a semiconductor wafer having a high flatness of an outer peripheral portion after double-side polishing, a carrier manufacturing method, a carrier evaluation method, and a semiconductor wafer polishing method.SOLUTION: In a carrier for double-side polishing having a holding hole for holding a semiconductor wafer, a difference in a carrier thickness at an inner wall position where the holding hole is defined and at a position 6 mm radially outside the holding hole from the inner wall is 1 μm or less.SELECTED DRAWING: Figure 4

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Inventors:
KUROIWA TAKESHI
KONDO KEI
Application Number:
JP2018078691A
Publication Date:
October 24, 2019
Filing Date:
April 16, 2018
Export Citation:
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Assignee:
SUMCO CORP
International Classes:
H01L21/304; B24B37/28
Domestic Patent References:
JP2018015877A2018-02-01
JP2010023217A2010-02-04
JP2011143477A2011-07-28
JP2006205265A2006-08-10
JP2015174168A2015-10-05
JP2004148497A2004-05-27
JP2017170536A2017-09-28
JP2005066773A2005-03-17
JP2011025322A2011-02-10
JP2013116508A2013-06-13
Foreign References:
WO2015136840A12015-09-17
US6454635B12002-09-24
Other References:
安永暢男, はじめての研磨加工, JPN6021043041, 20 April 2011 (2011-04-20), JP, pages 41 - 78, ISSN: 0004629691
安永暢男、高木純一郎, 精密機械加工の原理, JPN6021043040, 25 October 2002 (2002-10-25), JP, pages 160 - 163, ISSN: 0004629692
Attorney, Agent or Firm:
Kenji Sugimura
Mitsutsugu Sugimura
Keisuke Kawahara



 
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