Title:
【発明の名称】半導体パッケージ
Document Type and Number:
Japanese Patent JP2927010
Kind Code:
B2
Abstract:
In a semiconductor package in which a cover and a substrate are combined with each other in a sealed state, metallized portions consisting of a material of a high solder wettability are provided on the joint surface, which is opposed to the substrate, of the cover, outer side surfaces of the cover, and the portions of the inner side surfaces of the cover which are in the vicinity of the joint surface. These metallized portions are formed so that the height thereof on the outer side surfaces of the cover is larger than that on the inner side surfaces thereof. The metallized portions on the outer side surfaces are formed so that the height thereof at the corner portions of the cover is larger than that at the intermediate portions of the four sides thereof, and the metallized portions on the inner side surfaces are formed so that the height thereof at the intermediate portions of the four sides of the cover is larger than that at the corner portions thereof. This enables the excess and shortage of solder supplied to the joint portions of the substrate and cover constituting the semiconductor package to be prevented.
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Inventors:
MIURA SHINYA
KANDA KOZO
SHIRAI MITSUGI
KANDA KOZO
SHIRAI MITSUGI
Application Number:
JP3585091A
Publication Date:
July 28, 1999
Filing Date:
March 01, 1991
Export Citation:
Assignee:
HITACHI SEISAKUSHO KK
International Classes:
H01L23/02; H01L23/10; H01L23/42; H01L23/433; H01L25/065; (IPC1-7): H01L23/02
Domestic Patent References:
| JP2142536U |
Attorney, Agent or Firm:
Ogawa Katsuo