Title:
【発明の名称】キャッシュコントローラ
Document Type and Number:
Japanese Patent JP2952884
Kind Code:
B2
Abstract:
PURPOSE:To monitor the rewriting of a main memory without reducing the performance of a CPU by providing the cache controller with a valid bit register for storing the existence of the validity of address tags as the monitored result of rewriting in the main memory independently of an access from the CPU. CONSTITUTION:The cache controller includes a valid bit memory 5 for storing the existence of the validity of address tags 22, 32 for an access from the CPU to an address tag memory 1, the valid bit register 6 for storing the existence of the validity of the address tags 22, 32 in accordance with the monitored result of rewriting in the main memory independently of the access from the CPU and a logical circuit 4 for generating a hit signal 25 when the valid bit memory 5 and the valid bit register 6 indicate the validity of the address tags 22, 32 at the time of the access from the CPU. Consequently, the operation of the CPU can be prevented from being temporarily weighted by the monitoring operation of the main memory rewriting and the main memory rewriting can be monitored without reducing the performance of the CPU.
More Like This:
| JP2009277243 | COMPILER DEVICE AND OPERATING SYSTEM |
| JPS6266350 | CACHE MEMORY |
| JPS63245537 | INFORMATION PROCESSOR |
Inventors:
TANAKA YASUHARU
Application Number:
JP9794489A
Publication Date:
September 27, 1999
Filing Date:
April 17, 1989
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G06F12/08; (IPC1-7): G06F12/08; G06F12/08
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)