Title:
【発明の名称】出力ドライバ回路
Document Type and Number:
Japanese Patent JP3366484
Kind Code:
B2
Abstract:
PURPOSE: To connect plural circuits operated by different power supply voltages with a common bus. CONSTITUTION: When a signal S1 goes to H and a signal S2 goes to L, a PMOS 61 and an NMOS 63 are both turned off. Furthermore, the signal S1 at the H level is given to a gate G of a PMOS 62 via an NMOS 66. In this case, a PMOS 65 is nonconductive and an output terminal OUT 1 reaches a high impedance state. When a high power supply potential VDD is impressed to the output terminal OUT 1, the PMOS 65 is conductive and the high power supply potential VDD is fed to a gate G of the PMOS 62. Since the PMOS 62 is nonconductive, impression of the high power supply potential VDD to a drain D of the PMOS 61 is interrupted. Since the NMOS 66 is nonconductive, no high power supply potential VDD is impressed to the gate G of the PMOS 61 and the input of the S1 at the H level is kept received.
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Inventors:
Tsuneu Ishimasa
Application Number:
JP6820595A
Publication Date:
January 14, 2003
Filing Date:
March 27, 1995
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H01L21/8238; H01L27/092; H03K19/0175; H03K19/0948; (IPC1-7): H03K19/0175; H03K19/0948
Domestic Patent References:
| JP77411A |
Attorney, Agent or Firm:
Yasunari Kakimoto