Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2004241649
Kind Code:
A
Abstract:
To reduce the number of processes for forming a plurality of transistor areas whose breakdown voltages are different.
An N channel high breakdown voltage transistor area, a P channel type high breakdown voltage transistor area and an N channel low breakdown voltage transistor area are formed with a first oxide film 3 and an LOCOS oxide film 5, and both breakdown voltage transistor areas are formed with second oxide films 7A1, 7A2 and 7B thicker than the first oxide film 3 so that high breakdown voltages can be maintained, and N+ type source/drain areas 23 and 24 are simultaneously formed. Also, the P channel type high breakdown transistor area is formed with a second oxide film 7B so that the protection of an offset part can be attained.
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Inventors:
TANIGUCHI TOSHIMITSU
GOSHIMA KAZUTOMO
GOSHIMA KAZUTOMO
Application Number:
JP2003029856A
Publication Date:
August 26, 2004
Filing Date:
February 06, 2003
Export Citation:
Assignee:
SANYO ELECTRIC CO
International Classes:
H01L21/8234; H01L21/8238; H01L27/088; H01L27/092; (IPC1-7): H01L21/8234; H01L21/8238; H01L27/088; H01L27/092
Attorney, Agent or Firm:
Masamasa Shibano
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