Title:
集積回路におけるランディングパッド構成体の製造方法
Document Type and Number:
Japanese Patent JP4156044
Kind Code:
B2
Abstract:
A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is formed in the first opening and on a portion of the first dielectric layer adjacent the first opening. The dual landing pad is preferably formed from two polysilicon landing pads with an oxide formed in between a portion of the two polysilicon layers and over the first polysilicon layer. This landing pad will enhance the planarization of the wafer at this stage of the manufacturing and tolerate misalignment of subsequently formed metal contacts without invading design rules.
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Inventors:
Roy N. Newen
Frank Earl. Bryant
Arthur Py. Balasinski
Frank Earl. Bryant
Arthur Py. Balasinski
Application Number:
JP33354695A
Publication Date:
September 24, 2008
Filing Date:
December 21, 1995
Export Citation:
Assignee:
STMicroelectronics,Inc
International Classes:
H01L21/28; H01L21/285; H01L21/3205; H01L21/768; H01L23/52; H01L29/417
Domestic Patent References:
| JP4038853A | ||||
| JP5160024A | ||||
| JP6097108A | ||||
| JP5013596A | ||||
| JP4279057A | ||||
| JP8139193A | ||||
| JP6350051A |
Attorney, Agent or Firm:
Masaaki Kobashi