Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4209064
Kind Code:
B2
Abstract:
A semiconductor memory device of a dynamic type having an interface of a static-type semiconductor memory device includes a memory cell array, and a control circuit controlling a read operation to be initiated in response to a predetermined signal externally applied thereto before a read or write command is externally applied to the control circuit.
More Like This:
| JP2002063792 | SEMICONDUCTOR MEMORY AND ITS CONTROL METHOD |
| JP4217848 | Refresh control circuit |
| JP2002260383 | SEMICONDUCTOR MEMORY |
Inventors:
Hitoshi Ikeda
Application Number:
JP2000054881A
Publication Date:
January 14, 2009
Filing Date:
February 29, 2000
Export Citation:
Assignee:
Fujitsu Microelectronics Limited
International Classes:
G11C11/403; G11C7/00; G11C7/22; G11C11/408; G11C11/409
Domestic Patent References:
| JP63155495A | ||||
| JP63155494A | ||||
| JP4279945A |
Attorney, Agent or Firm:
Tadahiko Ito