Title:
ペアトランジスタの配列を高密度とする半導体記憶装置
Document Type and Number:
Japanese Patent JP4470159
Kind Code:
B2
Abstract:
A semiconductor storage device in which a pair of wiring lines extending in a first direction are arranged repeatedly with a predetermined pitch, comprising: a group of pair transistors in which a plurality of pair transistors is arranged according to a repetition unit with a predetermined pattern, the pair transistors composed of a MOS transistor of which a gate is connected to one line of the pair of wiring lines and of another MOS transistor of which a gate is connected to the other line of the pair of wiring lines, wherein the repetition unit of the group of pair transistors includes a plurality of the pair transistors such that two MOS transistors are adjacent to each other in the first direction, and at least one pair of pair transistors such that two MOS transistors are not adjacent to each other and diagonally opposite to each other.
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Inventors:
Junichi Sekine
Application Number:
JP2004166349A
Publication Date:
June 02, 2010
Filing Date:
June 03, 2004
Export Citation:
Assignee:
Elpida Memory Co., Ltd.
International Classes:
H01L21/8242; G11C5/06; G11C11/401; G11C11/412; H01L27/108
Domestic Patent References:
| JP2003068880A | ||||
| JP2003234418A | ||||
| JP2126672A | ||||
| JP2181964A | ||||
| JP6013574A |
Attorney, Agent or Firm:
Kohei Shuto