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Title:
PLLにおける節電用バイアス切断
Document Type and Number:
Japanese Patent JP4607410
Kind Code:
B2
Abstract:
A power conserving phase-locked loop achieves power savings by adding a switch which selectively enables the bias current for the charge pump associated with the phase comparator of the phase-locked loop. The switch is connected by a logic circuit to a counter that tracks the expected arrival time of a signal edge of the reference signal. Immediately prior to the arrival of the expected signal edge, the switch is enabled, thereby creating and applying the bias current to activate the charge pump in the event that a correction is needed to maintain the "lock" in the phase-locked loop. When the signal edge passes, the bias current is turned off again before the arrival of the next signal edge. This switching may result in a ten percent duty cycle in the biasing current, resulting in approximately a ninety percent power savings. The phase-locked loop may be used for a variety of applications, such as a frequency synthesizer in a receiver chain of wireless communications mobile terminals, where power consumption is a concern.

Inventors:
Clemmer, Nicolaus
White, Stephen, Elle
Application Number:
JP2001552527A
Publication Date:
January 05, 2011
Filing Date:
January 02, 2001
Export Citation:
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Assignee:
ERICSSON INC.
International Classes:
H03L7/093; H03L7/08; H03L7/089; H03L7/14; H03L7/18; H04B1/26; H04B1/40; H04L7/033; H03L7/095; H04B1/16
Domestic Patent References:
JP11234126A
JP10190451A
JP9153796A
JP7030416A
JP7079158A
JP2000151398A
Attorney, Agent or Firm:
Yasunori Otsuka
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura
Osamu Shimoyama
Nagakawa Yukimitsu
Youhei Kawabata
Kato Takushi
Yasuhiro Sakata
Masafumi
Hayashi Zouzo