Title:
極性補正回路
Document Type and Number:
Japanese Patent JP6603310
Kind Code:
B2
Abstract:
A power unbalance mitigating polarity correction circuit is presented comprising a first and a second polarity correction circuit, each comprising: an input for receiving an input current, an output for providing a rectified output current, at least a first current path, for conducting the received current when the received current is of a first polarity, and a second current path, for conducting the received current when the received current is of a second polarity, wherein the first current path comprises a passive rectification component as an asymmetric conductance component of a first type and the second current path comprises an active rectification component as an asymmetric conductance component of a second type different from the first type; the power unbalance mitigating polarity correction circuit further comprising a controller, wherein the controller is arranged for controlling the active rectification component to operate in a power unbalance mitigation mode when the current received by the first polarity correction circuit is conducted over the first current path of the first polarity correction circuit and the current received by the second polarity correction circuit is conducted over the second current path of the second polarity correction circuit.
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Inventors:
Vent Mattias
Yeseboat Rennat
Yeseboat Rennat
Application Number:
JP2017511984A
Publication Date:
November 06, 2019
Filing Date:
August 27, 2015
Export Citation:
Assignee:
SIGNIFY HOLDING B.V.
International Classes:
H02J1/00; G06F1/26; H02H11/00
Domestic Patent References:
| JP2008529462A | ||||
| JP2009011093A | ||||
| JP2011514801A |
Foreign References:
| EP2728793A2 | ||||
| US20140203651 | ||||
| US20130307427 | ||||
| US5963441 |
Attorney, Agent or Firm:
Sakiko Shibata