Title:
同期整流ＦＥＴ駆動回路
Document Type and Number:
Japanese Patent JP6660699
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a synchronous rectification FET driving circuit which suppresses disturbance of an output voltage on a startup operation, while reducing fear that the voltage between a drain and a source of a synchronous rectification FET exceeds a rating voltage on the startup of a stabilized power supply.SOLUTION: A synchronous rectification FET driving circuit comprises: a control circuit 34 that outputs two PWM signals; a secondary side driver 32 that drives a synchronous rectification FET; a logic circuit 35 that outputs a logical sum of the two PWM signals; a signal delay circuit 36 that delays an output signal of the logic circuit 35 by a first predetermined time; and a voltage detector 391 that detects an activation of the control circuit 34 and delays the signal by a second predetermined time. The secondary side driver 32 stops the signal output while the output signal of the signal delay circuit 36 is at a low level. The control circuit 34 increases a dead time range until the second predetermined time is elapsed, and the voltage detector 391 outputs a high level signal after the output signal of the signal delay circuit 36.SELECTED DRAWING: Figure 1
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Inventors:
Tomoji Matsushita
Masamichi Fukuda
Toshimasa Sugihara
Masamichi Fukuda
Toshimasa Sugihara
Application Number:
JP2015191558A
Publication Date:
March 11, 2020
Filing Date:
September 29, 2015
Export Citation:
Assignee:
FDK Corporation
International Classes:
H02M1/08
Domestic Patent References:
| JP2003143846A | ||||
| JP2014236596A | ||||
| JP2005304279A |
Foreign References:
| US20070115703 |
Attorney, Agent or Firm:
Koji Nagato