Title:
半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP6802454
Kind Code:
B2
Abstract:
An active region through which current flows in a semiconductor device includes an n−-type silicon carbide epitaxial layer formed on a front surface of an n+-type silicon carbide semiconductor substrate; a p-type layer becoming a channel region; a trench formed so as to be in contact with a p-type layer and having an oxide film and a gate electrode embedded therein; a p+-type layer arranged beneath the trench and between trenches; an n−-type layer in contact with the p-type layer, a p+-type layer, and the trench, and arranged in contact with a p+-type layer or on a surface side of the semiconductor substrate; an n-type layer in contact with the n−-type silicon carbide epitaxial layer and the p+-type layer, and having an impurity concentration higher than that of the n−-type layer and that of the n−-type silicon carbide epitaxial layer.
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Inventors:
Kobayashi Yusuke
Hiroshi Shiomi
Shinya Kyogoku
Shinsuke Harada
Akinori Kinoshita
Hiroshi Shiomi
Shinya Kyogoku
Shinsuke Harada
Akinori Kinoshita
Application Number:
JP2016155089A
Publication Date:
December 16, 2020
Filing Date:
August 05, 2016
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
National Institute of Advanced Industrial Science and Technology
Sumitomo Electric Industries, Ltd.
National Institute of Advanced Industrial Science and Technology
Sumitomo Electric Industries, Ltd.
International Classes:
H01L29/78; H01L21/336; H01L29/06; H01L29/12
Domestic Patent References:
| JP2015072999A |
Foreign References:
| WO2016002766A1 | ||||
| WO2017064948A1 |
Attorney, Agent or Firm:
Akinori Sakai