Title:
【発明の名称】配線処理方式
Document Type and Number:
Japanese Patent JPH0812884
Kind Code:
B2
Abstract:
PURPOSE:To increase processing speed, and optimize wiring performance, by unnecessitating the condition resetting for wiring region accompanied by the conversion of each pair layer, and enabling the reference of layers except the pair layer. CONSTITUTION:By a virtual wiring channel setting means 1, the following virtual layer is set, and by using said virtual layer and a second layer, a two-layer virtual wiring channel is set. The virtual layer has an X direction virtual wiring track equivalent to sum of the number of X direction tracks on a first layer and the number of X direction tracks on a third layer, and a Y direction virtual wiring track corresponding with a Y direction track on the first layer and a Y direction track on the third layer. A two-layer wiring means 4 sets an X direction virtual wiring track corresponding with the first layer as forbidden wiring by a first wiring forbidding means 2, and constitutes a two-layer wiring in the virtual wiring channel. Then, the two-layer wiring means 4 sets the X direction virtual wiring track corresponding with the third layer as forbidden wiring by a second wiring forbidding means 3, and constitutes a two-layer wiring in the virtual wiring channel. A converting means 5 converts through holes between the virtual layer and the second layer, and converts the two- layer wiring to a three-layer wiring, thereby reducing processing time.
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Inventors:
Shigeyoshi Tawada
Application Number:
JP29824487A
Publication Date:
February 07, 1996
Filing Date:
November 26, 1987
Export Citation:
Assignee:
NEC
International Classes:
H01L21/3205; G06F17/50; H01L21/82; H01L23/52; H05K3/00; (IPC1-7): H01L21/82; G06F17/50; H05K3/00
Other References:
樹下行三編論理装置のＣＡＤ昭和５６年３月２０日，社団法人情報処理学会発行Ｐ．４３−５０
Attorney, Agent or Firm:
Sakai Hiromi
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