PURPOSE: To eliminate the effect of signal delay time, by reducing the logical amplitude given to an input terminal of an ECL gate.

CONSTITUTION: A transistor Q1 is turned off when an input terminal IN1 is opened. Thus, the potential of an output N1 of an input circuit depends on a resistor R1 and a constant power supply IEF1 and is constant. When a high potential is inputted to the input terminal IN1, the TRQ1 turns on, the TR acts like an emitter follower and the potential at the output N1 is increased. Since the output N1 of the input circuit is clamped, the amplitude of the input signal to the ECL gate circuit is reduced more than the amplitude of the input signal to the input terminal IN1. Thus, the charging time to a parasitic capacitance of the circuit is reduced.