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Title:
ACTIVE MATRIX SUBSTRATE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS
Document Type and Number:
Japanese Patent JP2008158189
Kind Code:
A
Abstract:

To perform exact gradation display by realizing a voltage writing operation and voltage holding suitable for the length of a sub-frame period.

First to k-th transistors are electrically connected to first to k-th transistors corresponding respectively thereto. One terminal of the first transistor is electrically connected to a data line and the other terminal of the first transistor is electrically connected to one of a first holding capacitor. The one terminals of the second to k-th transistors are electrically connected to the other terminals of the first to (k-1)st transistors which are fore stage transistors, respectively. The other terminals of the second to k-th transistors are electrically connected to one end of the second to k-th holding capacitors which correspond thereto, respectively. The other terminals of the first to k-th holding capacitors are electrically connected to potential lines.


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Inventors:
YAMAGUCHI YUKIHIRO
TAKAHASHI SHIGEYA
Application Number:
JP2006345927A
Publication Date:
July 10, 2008
Filing Date:
December 22, 2006
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
G09G3/36; G02F1/133; G09G3/20
Domestic Patent References:
JP2002108309A2002-04-10
JP2004361728A2004-12-24
JPH10214060A1998-08-11
Attorney, Agent or Firm:
Kazuya Nishi
Masatake Shiga
Masakazu Aoyama



 
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