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Title:
ADDRESS CIRCUIT
Document Type and Number:
Japanese Patent JPS6318591
Kind Code:
A
Abstract:

PURPOSE: To raise the potential of an X address signal line at high speed by connecting a pull up circuit to the X address signal line.

CONSTITUTION: In an address circuit using multi-address wirings and connecting a Y address signal line to the X address signal line through a transfer transistor, the potential of the X address signal line AX is raised at the high speed and the pull up circuit 14 is connected to the X address signal line AX in order to eliminate the delay in time in comparison with the rise in the potential of the Y address signal line AY. Namely, the pull up circuit is constituted of an inverter 12 and a NAND13, and the inverter 12 is constituted of an N channel transistor Q14 and a P channel transistor Q13 having a current capacity n times larger (n>1) than the current capacity of this transistor Q14.


Inventors:
NAKAIZUMI KAZUO
Application Number:
JP16300886A
Publication Date:
January 26, 1988
Filing Date:
July 10, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
G11C11/413; G11C11/34; G11C11/407; G11C11/408; (IPC1-7): G11C11/34
Domestic Patent References:
JPS55150189A1980-11-21
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)