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Title:
BINARY IMAGE INTERPOLATING CIRCUIT
Document Type and Number:
Japanese Patent JPH03179490
Kind Code:
A
Abstract:

PURPOSE: To generate an interpolation signal whose edge parts are improved by detecting a slanting edge pattern by using pieces of picture element information on a 1st and a 2nd scanning line, making the number of picture elements of an interpolation scanning line larger than the number of picture elements of the 1st and 2nd scanning lines, and generating picture element information on the interpolation scanning line according to a detection output.

CONSTITUTION: A binary image which is inputted from a terminal 104 is converted by a 1H(one horizontal scanning period) delay circuit 105 and D flip-flops 106 - 109 so that two vertical lines and two horizontal picture elements can be referred to, and their signals are sent to a block 101. The block 101 detects three kinds of partial patterns by AND elements 118 - 120 since the slanting edge pattern consists of the three kinds of partial patterns. According to the detection output of the detecting means, a means which generates the oversampled interpolation signal is used to generates two interpolation images of the other field for interlaced scanning. Consequently, the binary frame image having slanting edges improved is obtained.


Inventors:
NAKAYAMA TADAYOSHI
KAWAHARA NORIHIRO
Application Number:
JP31992989A
Publication Date:
August 05, 1991
Filing Date:
December 08, 1989
Export Citation:
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Assignee:
CANON KK
International Classes:
G06T3/40; G09G1/16; G09G5/00; G09G5/36; H04N1/387; H04N5/44; H04N7/01; (IPC1-7): G09G1/16; G09G5/00; G09G5/36; H04N1/387
Attorney, Agent or Firm:
Giichi Marushima (1 person outside)