PURPOSE: To attain the pull in at a correct bit timing by providing a bit comparison means and a deciding means deciding the coincidence/dissidence of the bit timing of 1st and 2nd data strings at a period of one over an integral number of the frame of the data strings.

CONSTITUTION: Suppose that a bit timing difference is caused in the input data strings 11, 12 at a moment, the bit timing difference is detected by a bit comparator 1 and a dissidence detection pulse is outputted to a bit selection circuit 2 as a bit comparison signal 13. The bit selection circuit 2 samples the data strings at a period of one over an integral number of the frame of the input data strings. Then a dissidence deciding circuit 6 applies the decision of coincidence/dissidence from the result of bit comparison to be sampled. As a result, the decision such that the bit timing of the data strings is coincident regardless of being deviated with each other due to light load of the input data strings 11, 12, is reduced and the synchronization is taken in a correct bit timing.