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Title:
BONDING METHOD OF S* CHIP AND SUBSTRATE
Document Type and Number:
Japanese Patent JPS5314564
Kind Code:
A
Abstract:
PURPOSE:To reduce the temperature rise during operating by providing dummy terminals on the insulation layer of a Si substrate surface thereby increasing the reliability of strength resistance and temperature resistance cycles and providing a cooling plate on the rear of the substrate and connecting said plate to the dummy terminals.

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Inventors:
SOGA TASAO
YASUDA TOMIROU
TAKAHASHI KAZUYA
ODAWARA KOUZOU
Application Number:
JP8823176A
Publication Date:
February 09, 1978
Filing Date:
July 26, 1976
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/60; H01L21/58; (IPC1-7): H01L21/58



 
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