Title:
FORCED PAGE ZERO PAGING SYSTEM FOR MICRO CONTROLLER USING DATA RAM
Document Type and Number:
Japanese Patent JP3220714
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To add an exclusive bit to an operation code decoding column and to force data access generated in the page '0' of a random access memory(RAM) for an instruction.
SOLUTION: A user can select an arbitrary page and can directly access to a specified function register positioned in the page '0' of RAM 22 or to a register variable. Setting of an exclusive bit does not affect present operation of a micro controller 20, or setting of the bit does not correct and address which is stored in an operation code instruction executed at present by the micro controller and is selected at present.
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Inventors:
Randy El. Yak
Application Number:
JP22514098A
Publication Date:
October 22, 2001
Filing Date:
July 03, 1998
Export Citation:
Assignee:
Microchip Technology, Incorporated
International Classes:
G06F9/32; G06F9/30; G06F9/318; G06F9/34; G06F12/02; G06F12/06; H02J13/00; (IPC1-7): G06F9/34; G06F12/02
Domestic Patent References:
| JP4287231A | ||||
| JP60230246A | ||||
| JP5525179A |
Other References:
【文献】米国特許6055211(US,A)
【文献】欧州特許出願公開889393(EP,A2)
【文献】欧州特許出願公開889393(EP,A2)
Attorney, Agent or Firm:
Hirotsugu Yoshioka (2 outside)