To provide a circuit arrangement for a CPU memory system having ready signal control and easily improve performance of a CPU during reading and writing of data.

The circuit arrangement has a controllable increment apparatus capable of outputting either one of an address outputted from the CPU or an increased address, an address memory storing the address outputted from the increment apparatus, and a comparator comparing the address stored in the address memory with an address outputted from the CPU in a subsequent clock cycle. The controllable increment apparatus is controlled by the comparator. By the controllable increment apparatus, the increased address is outputted when the compared addresses match, and the address supplied from the CPU is outputted when the compared addresses do not match.