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Title:
CIRCUITS AND METHOD FOR DIVIDING FREQUENCY
Document Type and Number:
Japanese Patent JP2008301488
Kind Code:
A
Abstract:

To provide circuit and a method for programmable integer clock division with 50% duty cycle.

The present invention relates to circuits and a method for dividing a frequency of an input signal by an integer divider value. The circuit generally comprises (a) a first frequency divider, including a first plurality of serially connected delay elements receiving the input signal and a first configurable feedback network, (b) a second frequency divider, including a second plurality of serially connected delay elements receiving an inverse of the input signal and a second configurable feedback network, (c) configurable logic configured to select and/or combine outputs of the first and second frequency dividers and to produce a frequency divided output signal, and (d) a programmable circuit configured to selectably configure the first and second configurable feedback networks and the configurable logic.


Inventors:
SCUTERI JEREMY
Application Number:
JP2008137661A
Publication Date:
December 11, 2008
Filing Date:
May 27, 2008
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
H03K23/64; H03K21/00; H03K23/66; H03L7/06; H03L7/08
Domestic Patent References:
JPH07154243A1995-06-16
JPH08340250A1996-12-24
JPH10135821A1998-05-22
JPH10276083A1998-10-13
JPS54112152A1979-09-01
JP2002043929A2002-02-08
JPH07154243A1995-06-16
JPH08340250A1996-12-24
JPH10135821A1998-05-22
JPH10276083A1998-10-13
JPS54112152A1979-09-01
JP2002043929A2002-02-08
Attorney, Agent or Firm:
Masahiko Ueyanagi
Osamu Suzawa
Kazuhiko Miyasaka



 
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