PURPOSE: To reduce a phase shift in clock switching by monitoring a clock from the opposite high frequency clock source mutually, selecting the clock from either block source according to the monitoring result, and then dividing its frequency and outputting the result.

CONSTITUTION: A switching circuit 4a is controlled with the output (c) of a clock break detecting and holding circuit 3a to outputs the other clock when the clock is normal or its clock when abnormal. When the frequency division ratio of a frequency dividing circuit 5a is set to 1/2, the output (d) of the switching circuit 4a shifts in phase by a 1/4 period owing to switching at the time of a break of a clock (a), but the output (e) of the frequency dividing circuit 5a is out of phase only by 1/8 as much as a period T'. For the purpose, the rate of the clock is increased and the frequency division ratio is also increased to obtain a clock circuit output (e) which has a small phase shift.