To provide a clock frequency division circuit (1) with an n-bit counter which outputs frequency-divided outputs at constant timings irrespective of a division ratio.

A decoder (4) serves to select a desired division ratio 1/m, and an n-bit counter 2 has the function of counting by adding an increment of 2ⁿ/m (3) corresponding to the division ratio m, so that outputs depending on the division ratio are all output from the most significant counter, where n, m are positive integers satisfying n>2, m≥2 and 2ⁿ/2≥m.