PURPOSE: To enable to obtain a high degree of integration for the titled device by a method wherein the layout for a CMOS inverter is contrived in such a manner that the channel length direction of the MOSFET for load and that of the MOSFET for driving make crossing at a right angle.
CONSTITUTION: As the drain and the source of the MOSFET for a p-channel type load are used as p+ regions 15 and 16 respectively, and the section between these p+ regions 15 and 16 is used as the channel of the current located between the drain and the source, a layout is made out in such a manner that the channel direction of them will be brought in vertical direction and that the channel length direction of the MOSFET 1 and 2 will be crossed making a right angle. By making out the layout of memory cells as above-mentioned, the built- in MOSFET 1 for load can be formed in an excellent reproducibility even when the channel length of the MOSFET 2 for driving is reduced to a submicron level as the microscopic formation of the cell progresses without depending upon the accuracy of mask-matching, thereby enabling to improve the degree of integration of the CMOS inverter pattern.
ANAMI KENJI
SHINOHARA HIROSHI
