COMPUTATION MODULE TO COMPUTE MULTI-RADIX BUTTERFLY TO BE USED IN DTF COMPUTATION

Japanese Patent JP2010016830

A

To provide a multi-radix butterfly computation module, keeping a low complexity, that is able to compute butterflies on a flow when computing different sizes of DFT (Discrete Fourier Transform).

The method proposes a single unit composed with a series of elementary computation units. Each computation unit aims at computing the product of one row of a matrix of order (r) with a column vector. This unit is able to compute butterflies up to size (r), some elementary computation units being unused for lower radix.

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BOUTTIER ARNAUD
NOURISSON XAVIER

JP2009160542A

January 21, 2010

July 07, 2009

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MITSUBISHI ELEC R&D CT EUROPE

H04J11/00

JP2005522804A	2005-07-28
JPH07200543A	1995-08-04
JP2007221596A	2007-08-30
JPH0918443A	1997-01-17

JPN6013030680; Ｋ．　Ｈ．　ＣＨＥＮ，　Ｙ．　Ｓ．　ＬＩ: 'Ａ　ｍｕｌｔｉ-ｒａｄｉｘ　ＦＦＴ　ｐｒｏｃｅｓｓｏｒ　ｕｓｉｎｇ　Ｐｉｐｅｌｉｎｅ　ｉｎ　Ｍｅｍｏｒｙ-ｂａｓｅｄ　Ａｒｃｈｉｔｅｃｔｕｒｅ　（ＰＩＭＡ）　ＦＯＲ　ＤＶＢ-Ｔ／Ｈ　ｓｙｓｔｅｍｓ' Ｍｉｘｅｄ　Ｄｅｓｉｇｎ　ｏｆ　Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔｓ　ａｎｄ　Ｓｙｓｔｅｍｓ，　２００８．　ＭＩＸＤＥＳ　２００８．　１５ｔｈ　Ｉｎｔｅｒｎａｔｉｏｎａｌ　Ｃｏｎｆｅｒｅｎｃｅ　ｏｎ , 200806, Ｐａｇｅｓ：　　　　５４９　-　５５３
JPN6013030681; Ｊｏｙａｎｔａ　Ｂａｓｕ，　Ｍｄ．　Ｓａｈｉｄｕｌｌａｈ，　Ａｍｉｔａｂｈａ　Ｓｉｎｈａ: 'Ａ　Ｎｅｗ　Ｇｅｎｅｒａｌｉｚｅｄ　Ｒｅｃｏｎｆｉｇｕｒａｂｌｅ　Ａｒｃｈｉｔｅｃｔｕｒｅ　ｆｏｒ　Ｄｉｇｉｔａｌ　Ｓｉｇｎａｌ　Ｐｒｏｃｅｓｓｏｒ' Ａｄｖａｎｃｅｄ　Ｃｏｍｐｕｔｉｎｇ　ａｎｄ　Ｃｏｍｍｕｎｉｃａｔｉｏｎｓ，　２００７．　ＡＤＣＯＭ　２００７．　Ｉｎｔｅｒｎａｔｉｏｎａｌ　Ｃｏｎｆｅｒｅｎｃｅ　ｏｎ , 200712

Michiharu Soga
Hidetoshi Furukawa
Suzuki Kenchi
Kajinami order
Masahiro Taguchi

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