Title:
CPU ADAPTER
Document Type and Number:
Japanese Patent JP3437429
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a CPU adapter capable of keeping the effective speed of existing BIOS at an appropriate value at the time of replacing the CPU of a personal computer with a CPU of higher performance.
SOLUTION: A conversion circuit 15 fetches address signals outputted from an MMX 10 to a decoder circuit, and concerning an area (FOOOOh-FFFFFh) relating to the BIOS, the circuit 15 masks CACHE signals for requesting a cache operation to a chip set 3 by an MMX 10 and masks KEN signals for reporting that the cache operation is possible to the MMX 10 by the chip set 3. Thus, transfer of data of an area between the MMX 10 and a main memory 2 is performed under a non-cache mode since cache operation is inhibited. Thus, without rewriting the BIOS, the effective speed of the BIOS is kept at an appropriate value and a personal computer main body is appropriately operated.
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Inventors:
Yamashita Steel
Application Number:
JP34333397A
Publication Date:
August 18, 2003
Filing Date:
December 12, 1997
Export Citation:
Assignee:
IO DATA DEVICE INC.
International Classes:
G06F12/08; H01R33/76; H01R33/94; H01R33/945; (IPC1-7): G06F12/08; H01R33/76; H01R33/94; H01R33/945
Domestic Patent References:
| JP5127994A | ||||
| JP8272736A | ||||
| JP612322A | ||||
| JP10214228A | ||||
| JP517975U |
Other References:
特集２ＣＰＵ＆ＲＡＭ強化月間，月刊アスキー，日本，株式会社アスキー，１９９３年 ３月 １日，第１７巻第３号，ｐ．１９８−２２０
Attorney, Agent or Firm:
Hisao Komori