Title:
DA変換回路、集積回路装置、電子機器
Document Type and Number:
Japanese Patent JP4412510
Kind Code:
B2
Abstract:
A D/A converter circuit which converts a digital signal of n bits into an analog signal and outputs the analog signal comprises: a plurality of D/A conversion processors, each of which converting a digital signal into an analog signal, the digital signal being made by dividing the n-bit digital signal at least into two; a plurality of output resistance regulators coupled to outputs of the plurality of respective D/A conversion processors; and an output signal generator generating the analog signal that forms an output of the D/A converter circuit based on outputs of the plurality of output resistance regulators. At least one of the D/A conversion processors is configured as a resistor string type D/A converter circuit including: a resistor string circuit which has a plurality of serially-coupled resistors and a plurality of switches, one end of each of the plurality of switches being coupled to one of coupling points of the plurality of resistors, and other ends of the plurality of switches being coupled together to form an output end; and a decode circuit which decodes the digital signal and generates a control signal that controls ON/OFF of the plurality of switches included in the resistor string circuit. Each of the plurality of output resistance regulators includes a variable resistance circuit which changes a resistance value to be substantially equal to an output resistance value of the D/A conversion processor, in accordance with a change in the output resistance value of the D/A conversion processor that is coupled to another output resistance regulator and configured as the resistor string type D/A converter circuit.
More Like This:
| JPH11163728 | D/A CONVERTER HAVING CURRENT CELL MATRIX TO IMPROVE LINEARITY AND ITS CONTROL METHOD |
| JP2017103783 | LOW GLITCH-NOISE DAC |
| JPH01133424 | DA CONVERTING CIRCUIT |
Inventors:
Kazuo Kawaguchi
Teruhiko Hayashi
Kunihiro Kajiwara
Teruhiko Hayashi
Kunihiro Kajiwara
Application Number:
JP2007331871A
Publication Date:
February 10, 2010
Filing Date:
December 25, 2007
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H03M1/68; H03M1/76; H03M1/78
Domestic Patent References:
| JP1133424A | ||||
| JP61107816A | ||||
| JP6209265A | ||||
| JP2001177410A | ||||
| JP11127080A |
Attorney, Agent or Firm:
Yukio Fuse
Mitsue Obuchi
Misa Nagata
Mitsue Obuchi
Misa Nagata