Title:
DATA RECEIVER
Document Type and Number:
Japanese Patent JP3515519
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a data receiver in which the scale of a serial-to-parallel conversion circuit for transmitting a Viterbi decode signal to a Leed-Solomon decoding circuit is reduced.
SOLUTION: For instance, in a BS(Broadcasting Satellite) digital broadcasting, there are one case where the Viterbi decode signal is outputted with one-bit width and the other case where the Viterbi decode signal is outputted with two-bit width according to a modulation method. When the Viterbi decode output is given with the one-bit width as serial data D0, a data converting part 242 alternately transmits the data to shift registers 256 and 258. The shift registers 256 and 258 then, alternately shift the data. When the Viterbi output signal is given with the two-bit width of D0 and D1, the shift registers 256 and 258 are synchronized with a serial clock and respectively shift the data D1 and D0.
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Inventors:
Nakajima, Hiroshi
Kita, Sachikazu
Kita, Sachikazu
Application Number:
JP2000400950A
Publication Date:
April 05, 2004
Filing Date:
December 28, 2000
Export Citation:
Assignee:
SANYO ELECTRIC CO LTD
International Classes:
H04N19/44; H03M9/00; H03M13/23; H03M13/29; H03M13/41; H04L27/22; H04N7/00; H04N19/00; H04N19/65; H04N19/89; (IPC1-7): H04L27/22; H03M9/00; H03M13/23; H03M13/29; H03M13/41; H04N7/00; H04N7/24
Attorney, Agent or Firm:
深見 久郎 （外３名）