PURPOSE: To reduce the necessary quantity of a storage area by shortening the time required for a processing when the partial delay time of a logic circuit is analyzed.

CONSTITUTION: This system is provided with an output direction propagation route analyzing means 3 analyzing a propagation characteristic from remarked parts in a logic circuit to the output direction of a signal in accordance with a connection relation within the logic circuit, an input direction propagation route analyzing means 4 analyzing the propagation characteristic from the remarked parts to the input direction of the signal in accordance with the connection relation and a remarked propagation route analyzing means 7 calculating the delayed time of the propagation route including the remarked parts as a process route based on the delay time calculated by these output direction propagation route analyzing means 3 and the input direction propagation route analyzing means 4.