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Title:
DIGITAL COMPARATOR CIRCUIT WITH HYSTERESIS
Document Type and Number:
Japanese Patent JPS59220837
Kind Code:
A
Abstract:

PURPOSE: To obtain comparison outputs with hysteresis by comparing the values in magnitude of plural input signals with one another and outputting a high-level signal to an output terminal, and inputting it to a set/reset FF circuit.

CONSTITUTION: (n) units of digital comparators 1 are cascaded successively in digit order and (n)-digit signals are compared. Further, output terminals 2 and 4 of the final-stage circuit 1 are connected to inputs of the set/reset FF5, which operates so as to give the hysteresis to the comparison outputs of the comparators. Namely, the circuits compare the values of input signals A and B to output high-level signals to output terminals 2 (A>B), 3 (A=B), and 4 (A<B), and they are inputted to the FF5. Thus, comparison outputs which are obtained by giving reference or set signals to be compared with some specific width and eliminated the influence of a flicker, namely, with hysteresis are obtained.


Inventors:
KITANO YOSHIMASA
Application Number:
JP9404883A
Publication Date:
December 12, 1984
Filing Date:
May 30, 1983
Export Citation:
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Assignee:
ULVAC CORP
International Classes:
G06F7/02; (IPC1-7): G06F7/02
Domestic Patent References:
JP40025084A
JPS5439963U1979-03-16
JPS514239B11976-02-09
JPS5520514A1980-02-14
Attorney, Agent or Firm:
Shigeru Yagita



 
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