Title:
DRY-ETCHING METHOD FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3485504
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a via hole of stable form while occurrence of bowing near the TEOS oxide film/SOG film interface is prevented by using a mixed gas containing a specified gas of specified flow-rate when forming the via hole, by dry etching, on an insulating film where an organic SOG film is provided on the TEOS oxide film.
SOLUTION: After forming a metal wiring which is to be a lower layer wiring 12 on a silicon substrate 11, a via hole 17 for conduction between an upper layer wiring and the lower layer wiring 12 is opened using a resist pattern 16 on an insulating film, where a plasma TEOS oxide film 13 and an organic SOG film 14 which are to be an interlayer insulating film are sequentially deposited on the metal wiring by dry etching. For dry etching with the via hole 17, the mixed gas of CHF3/CH2F2/CO is used. The mixing ratio of CH2 F2/(CHF3+CH2F2) is about 50% or more. With the mixing ratio as this, the via hole 17 is almost vertical.
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Inventors:
Naokatsu Ikegami
Application Number:
JP25586799A
Publication Date:
January 13, 2004
Filing Date:
September 09, 1999
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H01L21/302; C03C15/00; H01L21/3065; H01L21/3213; H01L21/768; H01L23/522; (IPC1-7): H01L21/3065; H01L21/3213; H01L21/768
Domestic Patent References:
| JP817928A | ||||
| JP859215A | ||||
| JP11176814A |
Other References:
【文献】国際公開99/021218(WO,A1)
Attorney, Agent or Firm:
Kenji Ohnishi