To decrease a through-current by providing a circuit that sets a level of an output signal depending on plural input signals when a clock signal is at a level inverse to a 1st level and a circuit that controls levels of the input signals in response to the lock signal to the dynamic logic circuit.

When a clock signal 160 is at a low level, a P-channel MOS transistor(TR) 100 is conductive to set an internal signal 171 at a high level. Then an inverter consisting of MOS TRs 120, 121 sets an output signal 170 to be at a low level. In this case, since an inverter consisting of MOS TRs 130, 131 sets an internal signal 161 to be at a high level, an N-channel MOS TR 111 is conductive. Since an input signal 151 is forcibly set to have a low level, an N-channel MOS TR 101 is cut off, resulting that a through-current flowing through MOS TRs 100, 103, 102, 101 is eliminated.