PURPOSE: To reduce a standby current by executing the pre-charging of a bit line pair during the active period of a selection signal for a row address.
CONSTITUTION: The pre-charging potential of a power supply voltage VCC/2 generated in a generating circuit 12 for a pre-charging potential is supplied to bit line pairs 1a, 1b during the active period of the selection signal for a row address by means of transistors 6a, 6a for pre-charging so as to execute pre-charging. Thus, by executing the pre-charging of the bit line pairs 1a, 1b during the active period, even when the defect of short-circuit occurs between the bit line pairs 1a, 1b, and a word line 2, a standby current is reduced since a leakage current does not flow in the resetting period. Desirably, the equalization of the bit line pairs 1a, 1b by means of transistors 7, 11 is started in the resetting period of the selection signal for row address and terminated in the active period.
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TAKEDA HITOSHI
KATAKURA MASAYUKI
HASHIGUCHI AKIHIKO
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