Title:
【発明の名称】半導体記憶装置およびその製造方法
Document Type and Number:
Japanese Patent JP3195785
Kind Code:
B2
Abstract:
PURPOSE:To reduce an are occupied by a memory cell and to improve reliability by forming an Si layer in a source.drain region of MOSTr through selective epitaxial technique and by forming a storage node and a bit line contact thereon. CONSTITUTION:An isolation insulating film 2 and a p-type diffusion layer 3 are formed inside a p-type Si substrate 1. After a gate insulating film 4 is formed, a polycryatalline Si layer is deposited, P-diffusion is carried out, an insulating film 6 on a gate is formed, and a film and a gate electrode 5 are patterned. P or As in ion-implanted using the electrode 5 as a mask to form an n-diffusion layer 8. Then, a gate sidewall film 7 is formed. An Si formation layer is formed through selective epitaxial growth method, P or As is implanted using the gate electrode 5 as a mask to form an n<+> diffusion layer 10 and a layer insulating film 11 is formed all over. A storage node contact 12 is opened on an Si growth layer 9. A storage node electrode 13, a capacitor insulating film 14, a plate electrode 15, an insulating film 16, a bit line contact 17, a bit line 18 and a layer insulating film 19 are formed.
Inventors:
Takashi Yamada
Fumio Horiguchi
Akihiro Nitayama
Hiroshi Takahashi
Fumio Horiguchi
Akihiro Nitayama
Hiroshi Takahashi
Application Number:
JP18433989A
Publication Date:
August 06, 2001
Filing Date:
July 17, 1989
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L27/04; H01L21/28; H01L21/768; H01L21/822; H01L21/8242; H01L23/522; H01L27/10; H01L27/108; (IPC1-7): H01L27/108; H01L21/822; H01L21/8242; H01L27/04
Domestic Patent References:
| JP2143456A | ||||
| JP63227062A | ||||
| JP62224973A | ||||
| JP63226955A | ||||
| JP1150363A | ||||
| JP63166271A |