Title:
ELECTRONIC CIRCUIT AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3961044
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To avoid reduction of the coverage by elongating a second opening to a region outside a first wiring so that a cover insulation film does not appear on the inner wall of the second opening at an outer region of the first wiring to avoid forming a recess into the inner wall of the region.
SOLUTION: An anodic oxide film 35b exposed at the bottom of contact holes C3 is removed by wet etching. In the section where the inner wall of the contact hole C3 is located on an inner region of a gate line 34b, the film 35b is side-etched. As the result, a recess 40 is formed into a lower part of the inner wall of the hole C3. In the section where the inner wall of the contact hole C3 is located outside the gate line 34b, the anodic oxide film on the surface of the gate wiring 34b is entirely removed to expose part of a gate insulation film 33b and part of a base SiO2 film 31 at both sides of the gate line 34b.
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Inventors:
Tatsuya Ohori
Tetsuro Hori
Tetsuro Hori
Application Number:
JP11930496A
Publication Date:
August 15, 2007
Filing Date:
May 14, 1996
Export Citation:
Assignee:
Sharp Corporation
International Classes:
G02F1/1343; H01L23/522; G02F1/136; G02F1/1362; G02F1/1368; H01L21/306; H01L21/336; H01L21/768; H01L21/8234; H01L23/498; H01L23/538; H01L27/088; H01L29/786; (IPC1-7): H01L21/768; G02F1/1343; G02F1/136; H01L21/306; H01L21/8234; H01L27/088; H01L29/786; H01L21/336
Domestic Patent References:
JP52010089A | ||||
JP6250216A | ||||
JP59195844A | ||||
JP7335756A | ||||
JP7106416A | ||||
JP60111442A | ||||
JP63143845A | ||||
JP4085856A | ||||
JP1280337A | ||||
JP7022507A | ||||
JP4092428A | ||||
JP9148271A | ||||
JP10070089A |
Attorney, Agent or Firm:
Kenzo Hara International Patent Office
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