To facilitate fault-tolerant operation by providing a network which mutually connects a central processor and an input/output device so that one of central processors gains communication access to one of input/output devices without requesting other's use.

The MPs 18 of subprocessor systems 10A and 10B connect an IEEE1149. one-test bus 17 registers used by the MPs 18 to elements of the subprocessor systems thorugh on-line access port interfaces included in the elements so as to transmit states and control information between the elements and MPs 18. The MPs 18 generate and send message packets to communicate with a CPU 12. The CPU 12, a router 14, and an I/O packet interface 16 are mutually connected by a TNet link L and have a two-way data communication.