PURPOSE: To realize full duplex data transmission, by multiplexly modurating data and clock signals issued from a master device and transmitting them as current change signals, and making a subdevice receive the signals and compulsively the output of the master device to a loaded state with the transmission data.
CONSTITUTION: In a master device ME, a clock pulse CLK from an oscillator OSC, a synchronizing signal SYN obtained from the count of the CLK, and a serial data signal DAT1 from a selector SEL1 are multiplexly modulated at a modulator MOD and applied to an operational amplifier OP. The output is inputted to transistors (TRs) Q1, Q2, to flow an output current to lines L1 and L2. In a subdevice SE, a transmission data signal SD2 turns on a TRQ3, which bridges over the lines L1 and L2, and the output current of the master device ME becomes compulsively loaded to change a control voltage of a constant current circuit of the master device. This change is detected at comparators CP1, CP2 as reception data, and the reception at the subdevice is detected by comparing a voltage across a resistor R4 with a reference voltage at a comparator CP3.
JPS5489411A | 1979-07-16 | |||
JPS5493303A | 1979-07-24 | |||
JPS49114308A | 1974-10-31 | |||
JPS51134502A | 1976-11-22 |