To provide a glitch elimination circuit in which a circuit scale and power consumption can be reduced for eliminating glitches which mix in the input signal.

This glitch elimination circuit consists of a delay circuit 23 for adding a delays that is larger than the glitch width mixed in input data (Y), a comparator circuit 22 for comparing the logical value of the input data (Y) with the logical value of output data (Z) and deciding agreement/ disagreement, and a latch circuit 24 to which delay data (DY) outputted from the delay circuit 23 and the decision results (GY) of the comparator circuit 22 are inputted and which holds the delay data (DY), when the decision results (GY) of the comparator circuit 22 disagree and the output data (Z), when the decision results (GY) agree and outputs output data (Z) from an output terminal 25.