PURPOSE: To obtain a master-slave JKFF circuit which is operated stably at a high speed with a single-phase clock by constituting a gate circuit in two levels.

CONSTITUTION: The BFL system used desirably in a normally turned-on GaAs integrated circuit is adopted as a gate circuit system, and positive potential is given to VDD1∼VDD8 and negative potential is given to VSS1∼VSS4 at an operation time. Since the gate circuit is constituted in two levels in this circuit system, the number of gates to be inverted at the operation time is smaller than that in an all NOR constitution circuit, and consequently, the operation is performed at a high speed. Further, the circuit can be operated with the single- phase clock.